Plasma Etching Patents (Class 438/9)
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Patent number: 6689521Abstract: The present invention provides for a method and an apparatus for controlling plasma photoresist removal processes. At least one manufacturing run of semiconductor devices is processed. Environmental data is acquired in response to processing the semiconductor devices. Metrology data is acquired in response to processing the semiconductor devices. The method further comprises performing residual gas analysis based upon the acquired environmental data and the acquired metrology data.Type: GrantFiled: March 15, 2002Date of Patent: February 10, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Greg Goodwin
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Patent number: 6663784Abstract: A method is proposed for producing three-dimensional structures, especially microlenses, in a substrate using an etching process, at least one original shape having a known original surface shape being present initially on the substrate in a plurality of places. The etching process has at least one first etching removal rate a1 and a second etching removal rate a2 which are material-dependent, and of which at least one is changeable as a function of time. The original shape is converted to a target shape by the etching process, the original surface shape of the original shape and the target surface shape of the target shape to be reached being known before the beginning of the etching process. In order to achieve the target surface shape, at least one of the etching rates a2 or a1 is set by a change of at least one etching parameter calculated before the beginning of the etching process as a function of the etching time.Type: GrantFiled: February 4, 2002Date of Patent: December 16, 2003Assignee: Robert Bosch GmbHInventors: Nils Kummer, Roland Mueller-Fiedler, Klaus Breitschwerdt, Andre Mueller, Frauke Driewer, Andreas Kern
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Publication number: 20030226821Abstract: An automated process control system configured for controlling a plasma processing system having a chamber, the chamber being configured for processing a substrate. The automatic process control system includes a first sensor disposed within the chamber, the first sensor being configured for making a first plurality of measurements pertaining to a first parameter associated with a structure disposed at least partially within the chamber. The performing the first plurality of measurements is performed during the processing of the substrate. The automatic process control system further includes first logic coupled to receive the first plurality of measurements from the first sensor. The first logic is configured for analyzing using SPC methodologies the first plurality of measurements during the processing.Type: ApplicationFiled: June 7, 2002Publication date: December 11, 2003Inventors: Chung-Ho Huang, John A. Jensen
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Publication number: 20030228532Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.Type: ApplicationFiled: May 1, 2003Publication date: December 11, 2003Applicant: Applied Materials, Inc.Inventors: David S.L. Mui, Wei Liu, Hiroki Sasano
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Patent number: 6660651Abstract: A process tool comprised of an adjustable wafer stage and various methods and systems for performing process operations using same is disclosed herein. In one illustrative embodiment, the process tool is comprised of a process chamber, and an adjustable wafer stage in the process chamber to receive a wafer positioned thereabove, the wafer stage having a surface that is adapted to be raised, lowered or tilted. In further embodiments, the process tool further comprises at least three pneumatic cylinders or at least three rack and pinion combinations, each of which are operatively coupled to the wafer stage by a ball and socket connection.Type: GrantFiled: November 8, 2001Date of Patent: December 9, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Richard J. Markle
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Patent number: 6657719Abstract: A device for analyzing plasma enclosed in a chamber. The device has a lens array which has a plurality of lens array lenses. The lens array lenses are located in a position so that the line of sight for each lens array lens intersects one another at a single point in front of the lens array. Each lens array lens is also located in a position so that each lens array lens is focused near a rear wall of the chamber. Behind each lens array lens is a cable having a first end and a second end. The first end of the cable is located in a position to receive emission elements through the lens array lens. A collimating lens is located at the second end of the cable to couple the emission elements from the second end of the cable through a wavelength selective element. A recording device is located in a position to record the emission elements through the wavelength selective element.Type: GrantFiled: August 7, 2000Date of Patent: December 2, 2003Assignee: The United States of America as represented by the Department of CommerceInventor: Eric C. Benck
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Patent number: 6656374Abstract: Apparatus and method for post etching inspection of electrical circuits including an optical inspection assembly viewing an electrical circuit at various regions thereon and providing output indications of etching characteristics of the electrical circuit at the various regions and output circuitry receiving the output indications of etching characteristics of the electrical circuit at the various regions and providing an output indication of variations in the etching characteristics between at least some of the various regions.Type: GrantFiled: April 2, 2001Date of Patent: December 2, 2003Assignee: Orbotech Ltd.Inventor: Nissim Savareigo
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Publication number: 20030215963Abstract: A protective coating is provided herein and methods of using the protective coating for susceptors used in semiconductor deposition chambers are described. In the preferred embodiments, CVD chamber equipment, such as a susceptor, is protected from plasma etch cleaning. Prior to CVD of silicon nitride, the chamber equipment is first coated with an emissivity-stabilizing layer, such as silicon nitride. This layer is then superficially oxidized. After repeated cycles of deposited silicon nitride upon different substrates in sequence, the chamber is emptied of wafers and a plasma cleaning process is conducted. Plasma cleaning is preferably selective against the silicon oxynitride protective coating. After the plasma cleaning process, the emissivity-stabilizing layer is reapplied, oxidized, and a plurality of deposition cycles can commence again.Type: ApplicationFiled: May 17, 2002Publication date: November 20, 2003Inventors: Fred AmRhein, Christophe Pomarede
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Patent number: 6645781Abstract: In an integrated device, an etch is performed in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via and a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.Type: GrantFiled: April 29, 2002Date of Patent: November 11, 2003Assignee: Texas Instruments IncorporatedInventors: Ping Jiang, Heungsoo Park
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Patent number: 6641746Abstract: An integrated metrology and lithography/etch system and method (10) for micro-electronics device manufacturing. A process control neural network (30) is used to develop an estimated process control parameter (32) for controlling an etching process (28). The process control neural network is responsive to a multi-parameter characterization of a patterned resist feature MPC(PR) (16) developed on a substrate. The process control parameter is used as a feed-forward control for the etching process to develop an actual final mask feature. A multi-parameter characterization of the actual final mask feature MPC(HM) (36) is used as an input to a training neural network (40) for mapping to an ideal process control parameter. The ideal process control parameter is compared to the estimated control parameter to develop an error parameter (46), which is then used to train the process control neural network.Type: GrantFiled: September 28, 2001Date of Patent: November 4, 2003Assignee: Agere Systems, Inc.Inventors: Erik Cho Houge, John Martin McIntosh, Edward Alios Rietman
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Patent number: 6643559Abstract: The invention relates to a method for monitoring a production process, whereby several models are used for detecting a finish point. The results of the model are subsequently compared with one another and the best model therefrom is used in other production processes to detect a finish point. The inventive method provides the advantage that process changes resulting from chamber contaminations or sensor drift are compensated for by selecting the best model, thereby ensuring reliable finish point detection even in case of unfavorable process conditions.Type: GrantFiled: February 12, 2002Date of Patent: November 4, 2003Assignee: Infineon Technologies AGInventor: Ferdinand Bell
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Patent number: 6642150Abstract: A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.Type: GrantFiled: December 28, 1999Date of Patent: November 4, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chuan-Chieh Huang, Wen-Hsiang Tang, Ming-Shuo Yen, Chiang-Jen Peng, Pei-Hung Chen
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Publication number: 20030203515Abstract: A method for reducing preferential chemical mechanical polishing (CMP) of a silicon oxide filled shallow trench isolation (STI) feature during an STI formation process including providing a semiconductor wafer having a process surface including active areas for forming semiconductor devices thereon; forming a silicon oxynitride layer over the process surface for photolithographically patterning STI trenches around the active areas; photolithographically patterning STI trenches around the active areas for anisotropic etching; anisotropically etching the STI trenches extending through the silicon oxynitride layer into the semiconductor wafer; depositing a silicon oxide layer over the silicon oxynitride layer to include filling the STI trenches; and, performing a CMP process to remove the silicon oxide layer overlying the silicon oxynitride layer to reveal an upper surface of the silicon oxynitride layer.Type: ApplicationFiled: April 29, 2002Publication date: October 30, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Keng-Chu Lin, Chih-Ta Wu
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Publication number: 20030203516Abstract: In an integrated device, an etch is performed in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via and a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.Type: ApplicationFiled: April 29, 2002Publication date: October 30, 2003Inventors: Ping Jiang, Heungsoo Park
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Patent number: 6627555Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optically, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off.Type: GrantFiled: February 5, 2001Date of Patent: September 30, 2003Assignee: Saifun Semiconductors Ltd.Inventors: Boaz Eitan, Ilan Bloom
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Patent number: 6627548Abstract: The invention relates to a process for treating semiconductor substrates in which metal layers are exposed by removing one or more layers of the surface of a semiconductor substrate which have been applied to the metal layer, in which exposure takes place in a time sequence to a first part of the layer by a dry etching step and to a second part of the layer by a wet etching step.Type: GrantFiled: July 17, 2000Date of Patent: September 30, 2003Assignees: SEZ Semiconductor-Equipment Zubehor fur die Halbleiterfertigung AG, Infineon Technologies AGInventors: Hans-Jürgen Kruwinus, Geert De Nijs
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Patent number: 6627464Abstract: An adaptive plasma characterization system and method characterize a semiconductor plasma process using fuzzy logic and neural networks. The method includes the step of collecting input and output training data, where the input training data is based on variables associated with electrical power used to control a plasma chamber and results from execution of the plasma process. The method further includes the step of generating fuzzy logic-based input and output membership functions based on the training data. The membership functions enable estimation of an output parameter value of the plasma process, such that the membership functions characterize the plasma process with regard to the output parameter. Modifying the membership functions based on a neural network learning algorithm and output data provides ability to learn. Thus, etching process parameters such as etch rate, end point detection, and chamber maintenance can all be characterized in a manner that allows the system to operate autonomously.Type: GrantFiled: February 7, 2001Date of Patent: September 30, 2003Assignee: ENI Technology, Inc.Inventor: David J. Coumou
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Patent number: 6620631Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a blanket target layer. There is then formed over the blanket target layer a patterned mask layer. There is then measured, while employing an optical method, a linewidth of the patterned mask layer to determine a patterned mask layer measured linewidth. There is then determined a deviation of the patterned mask layer measured linewidth from a patterned mask layer target linewidth. There is then etched, while employing a plasma etch method, the blanket target layer to form a patterned target layer while employing the patterned mask layer as a etch mask layer.Type: GrantFiled: May 18, 2000Date of Patent: September 16, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hun-Jan Tao, Chia-Shiung Tsai, Anthony Yen
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Patent number: 6620520Abstract: A corrosion resistant component of semiconductor processing equipment such as a plasma chamber comprises zirconia toughened ceramic material as an outermost surface of the component. The component can be made entirely of the ceramic material or the ceramic material can be provided as a coating on a substrate such as aluminum or aluminum alloy, stainless steel, or refractory metal. The zirconia toughened ceramic can be tetragonal zirconia polycrystalline (TZP) material, partially-stabilized zirconia (PSZ), or a zirconia dispersion toughened ceramic (ZTC) such as zirconia-toughened alumina (tetragonal zirconia particles dispersed in Al2O3). In the case of a ceramic zirconia toughened coating, one or more intermediate layers may be provided between the component and the ceramic coating. To promote adhesion of the ceramic coating, the component surface or the intermediate layer surface may be subjected to a surface roughening treatment prior to depositing the ceramic coating.Type: GrantFiled: December 29, 2000Date of Patent: September 16, 2003Assignee: Lam Research CorporationInventors: Robert J. O'Donnell, Christopher C. Chang, John E. Daugherty
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Publication number: 20030166307Abstract: A method and a device for converting energyType: ApplicationFiled: January 17, 2002Publication date: September 4, 2003Inventors: Anthony C. Zuppero, Jawahar M. Gidwani
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Patent number: 6613588Abstract: The present invention is to detect particles suspended in a processing chamber using a single observation window and an optical system formed as a single unit and to provide precise detection of very weak particle-scattered light. When a thin film is being formed on an object to be processed in a processing chamber or if such a thin film is being processed, an optical guide module guides a laser beam from a laser light source separated from a laser illumination/scattered light detection optical system. The laser beam is guided to the laser illumination/scattered light detection optical system. The processing chamber is illuminated by the laser illumination/scattered light detection optical system via an observation window. The illumination light is scattered by particles in the processing chamber. Back-scattered light passing through the observation window is detected by the laser illumination/scattered light detection optical system.Type: GrantFiled: August 21, 2001Date of Patent: September 2, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Nakano, Toshihiko Nakata
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Publication number: 20030153102Abstract: A method for automated monitoring and controlling of a semiconductor wafer plasma etching process including collecting data versus time during a plasma etching process said data including information representative of a concentration of at least one pair of reactant and product species present during the course of the plasma etching process; calculating a selected ratio of at least one reactant species and one product species at selected time intervals in the plasma etching process to create real-time reactant-product ratio data; retrieving pre-determined reactant-product ratio data for the at least one reactant species and one product species for comparison with the real-time reactant-product ratio data; comparing the pre-determined reactant-product ratio data with the real-time reactant-product ratio data to determine a difference; and, adjusting at least one plasma process operating parameter to minimize the difference.Type: ApplicationFiled: February 14, 2002Publication date: August 14, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Hsien-Kuang Chiu
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Patent number: 6602793Abstract: An improved pre-clean chamber of a semiconductor processing system minimizes the generation of particulates during processing, thereby decreasing contamination levels that can adversely affect plasma vapor deposition film properties while also decreasing operational costs. The pre-clean chamber comprises an insulator collar that insulates the outside diameter surface of a wafer pedestal, thereby mitigating the etching of the wafer pedestal during etching. The pre-clean chamber further comprises a gas trench cover that directs a suitable etching gas from a gas inlet trench into streams that are focused up and towards the center of the chamber to reduce the extent to which gas bombards the chamber cover. The pre-clean chamber also comprises a bellows cover which protects the bellows of a wafer lift during etching, further reducing the dislodgment of particulates during etching.Type: GrantFiled: February 3, 2000Date of Patent: August 5, 2003Assignee: Newport Fab, LLCInventor: Sean Masterson
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Patent number: 6589858Abstract: A metal gate structure and method of making the same provides a tracer layer over a first metal or metal compound layer. When etching a metal gate, formed of tungsten, for example, with a first etchant chemistry optimized for etching tungsten, detection of the tracer layer through optical emission spectroscopy, for example, indicates the imminent clearing of the tungsten. A second etchant chemistry is then employed that is selective to the first metal or metal compound layer, such as TiN, overlying the gate dielectric. This provides a controlled etching of the TiN and thereby prevents degradation of the underlying gate dielectric material.Type: GrantFiled: June 7, 2002Date of Patent: July 8, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser
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Patent number: 6586262Abstract: The present invention is a method for end point detection where emission spectra are detected during etching of an object to be processed, such as a semiconductor wafer, by a spectrometer, and an end point of the etching is detected, comprising performing etching of a sample, corresponding to a product, prior to etching of a semiconductor wafer which is the product, sequentially measuring full-spectra of plasma, performing principal component analysis of the emission spectra using the emission intensities of all wavelengths of each of the full-spectra, holding the results as data, thereafter obtaining a principal component score for each of the full-spectra sequentially measured during etching of a semiconductor wafer to be manufactured on the basis of the emission intensities of all the wavelengths, and then detecting an end point of etching on the basis of a substantial change of the principal component score for each of the full-spectra sequentially measured.Type: GrantFiled: November 16, 2001Date of Patent: July 1, 2003Assignee: Tokyo Electron LimitedInventors: Susumu Saito, Shinji Sakano
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Patent number: 6585908Abstract: A process and apparatus for determining a real-time etching rate during a plasma mediated etching process. Real-time etching rate determination includes monitoring an interference pattern generated by a direct light beam and a reflected light beam from a wafer surface. A viewing angle for recording the interference pattern is nearly parallel to the wafer plane and at a fixed focal point on the layer to be removed. The direct light beam and reflected light beams are generated in situ during plasma processing.Type: GrantFiled: July 13, 2001Date of Patent: July 1, 2003Assignee: Axcelis Technologies, Inc.Inventors: Andre G. Cardoso, Alan C. Janos
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Publication number: 20030119215Abstract: A method of determining a performance of plasma etch equipment is provided. The method comprises extracting data that depend on the performance of plasma etch equipment, during etching of the wafer, for example by calculating an etch rate and by calculating a non-uniformity of a film being etched. After that, the extracted data are compared to predetermined data, and on the basis of a result of comparing the extracted data with predetermined data the performance of the plasma etch equipment is determined. Further, a system for determining a performance of plasma etch equipment is provided.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventor: Joseph Louis Petrucci
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Patent number: 6582618Abstract: A method is provided for determining an etch endpoint. The method includes collecting intensity data representative of optical emission spectral wavelengths during a plasma etch process. The method further includes calculating Scores from at least a portion of the collected intensity data using at most first, second, third and fourth Principal Components derived from a model. The method also includes determining the etch endpoint using Scores corresponding to at least one of the first, second, third and fourth Principal Components as an indicator for the etch endpoint.Type: GrantFiled: January 26, 2000Date of Patent: June 24, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Anthony John Toprac, Hongyu Yue
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Patent number: 6577915Abstract: A method and an apparatus for a semi-empirical process simulation using a calibrated profile simulator to create a reactor model which can predict neutral and ion flux distributions on a substrate as a function of the reactor settings include providing a set of conditions characterized by unique reactor settings. Wafers are processed under each condition. Etch or deposition rates and surface profiles are measured and used in the calibrated profile simulator to derive the flux distributions. The flux distributions data generated by the processes are then used to create a reactor model.Type: GrantFiled: June 30, 2000Date of Patent: June 10, 2003Assignee: Lam Research CorporationInventors: David Cooperberg, Vahid Vahedi
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Publication number: 20030104639Abstract: This disclosure is directed to a method of inspecting how contact holes or via holes are formed in a sample, such as a wafer. An electron beam is directed to the contact holes in succession. An absorbed current flowing through the sample is detected by a current amplifier. Data about the obtained absorbed current is stored in a memory. The electric current flowing through a reference sample and ground is measured, and the relation of the current to the etch depths of contact holes into the substrate is previously found. A control unit compares data about the measured current with the previously found relation and determines the depths of holes of interest into the substrate (i.e., inspects how they are etched).Type: ApplicationFiled: January 30, 2002Publication date: June 5, 2003Applicant: JEOL Ltd.Inventors: Naoki Kikuchi, Tsutomu Negishi, Yuki Ono
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Patent number: 6573120Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.Type: GrantFiled: June 7, 2002Date of Patent: June 3, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Il Jung, Jun-Taek Lee
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Publication number: 20030098290Abstract: An emission spectroscopic processing apparatus includes a spectroscope for spectrally separating input light emitted from a process unit into component spectra, a light receiving unit including a series of light receiving elements for detecting light quantities of the component spectra on a wavelength basis, a first signal hold unit for holding sequentially each of detection signals outputted from a subset of adjacent light receiving elements contained in series of light receiving elements during a first period, an adder unit for adding together the detection signals of adjacent light receiving elements of the light receiving unit inclusive of the held detection signals of the subset of adjacent light receiving elements, a second signal hold unit for holding sequentially sum outputs of the adder unit, and a signal processing unit for determining a state of the process unit on the basis of the output of the second signal hold unit.Type: ApplicationFiled: March 6, 2002Publication date: May 29, 2003Inventors: Tetsunori Kaji, Shizuaki Kimura, Tatehito Usui, Takashi Fujii
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Patent number: 6564114Abstract: A method is provided for determining an etch endpoint. The method includes collecting intensity data representative of optical emission spectral wavelengths during a plasma etch process. The method further includes analyzing at least a portion of the collected intensity data into at most first and second Principal Components with respective Loadings and corresponding Scores. The method also includes determining the etch endpoint using the respective Loadings and corresponding Scores of the second Principal Component as an indicator for the etch endpoint using real-time Principal Components Analysis applied to optical emission spectral data from a previous portion of the plasma etch process.Type: GrantFiled: January 26, 2000Date of Patent: May 13, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Anthony John Toprac, Joseph William Wiseman, Hongyu Yue
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Publication number: 20030087459Abstract: A system and method for determining endpoint detection in semiconductor wafer planarization is provided. The system and method provide a flexible solution that can compensate for baseline variability induced errors that may otherwise occur in endpoint detection. The system uses an endpoint detection signal that monitors the optical characteristics of the wafer being planarized. The system and method continue to monitor the detection signal during planarization until it meets endpoint criterion that indicates endpoint completion. When the endpoint criterion is reached, a new snapshot is taken from a previous time period and a new baseline is calculated. The endpoint detection signal is then recalculated based upon the new baseline and the recalculated detection signal is again compared to the endpoint criterion. If the recalculated endpoint detection signal again substantially meets the endpoint criterion then the detection of endpoint is confirmed.Type: ApplicationFiled: October 4, 2002Publication date: May 8, 2003Inventors: Thomas Laursen, Mamoru Yamayoshi
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Patent number: 6555397Abstract: Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.Type: GrantFiled: September 13, 2000Date of Patent: April 29, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Douglas J. Bonser, Matthew Purdy, James H. Hussey, Jr.
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Patent number: 6553332Abstract: A process chamber (12) is used for plasma etching of a wafer (21) disposed therein. A gas mixture supplied to the chamber eventually passes through openings (28) in a baffle plate (27). After the chamber has been cleaned, several test wafers are etched under conditions which are equivalent, except that a different gas pressure is used for each wafer. The effective etch rates are measured from these wafers, and used to extrapolate a reference curve (141) representing effective etch rate relative to pressure. During subsequent production use of the chamber, a similar procedure is periodically used to generate a test curve (142). The peak values (143, 144) of the reference and test curves are compared (147) to monitor process drift within the chamber. The peak values of respective curves obtained from two or more similar chambers can be compared to evaluate performance differences between the chambers.Type: GrantFiled: November 30, 2000Date of Patent: April 22, 2003Assignee: Texas Instruments IncorporatedInventor: Yaojian Leng
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Patent number: 6541282Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10 W to about 200 W or a pulsed RF power level from about 20 W to about 500 W. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.Type: GrantFiled: June 13, 2000Date of Patent: April 1, 2003Assignee: Applied Materials, Inc.Inventors: David Cheung, Wai-Fan Yau, Robert P. Mandal, Shin-Puu Jeng, Kuo-Wei Liu, Yung-Cheng Lu, Michael Barnes, Ralf B. Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon
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Publication number: 20030052083Abstract: A substrate processing apparatus has a chamber having a substrate transport to transport a substrate onto a substrate support in the chamber, a gas supply to provide a gas in the chamber, a gas energizer to energize the gas, and an exhaust to exhaust the gas. A detector is adapted to detect a first intensity of a first wavelength of a radiation emission from an energized gas in the chamber and generate a first signal in relation to the first intensity and to detect a second intensity of a second wavelength of the radiation emission and generate a second signal in relation to the second intensity. A controller receives the first and second signals from the detector, performs a mathematical operation on the first and second signals to determine a value related to a condition of the chamber, and treats the chamber in relation to the value by providing instructions to operate one or more of the substrate transport, substrate support, gas supply, gas energizer and gas exhaust.Type: ApplicationFiled: May 14, 2001Publication date: March 20, 2003Inventors: Nam-Hun Kim, Chong Hwan Chu
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Publication number: 20030052085Abstract: An RF power supply system (200) for use with an electrode (60) in a plasma reactor system (10) capable of supporting a plasma (32) with a plasma load impedance (ZR), wherein the electrode comprises a plurality of electrode segments (62a,62b, . . . , 62n). The system comprises a master oscillator (210), and a plurality of RF power supply subsystems (220a, 220b, . . . 220n) each electronically connected thereto, and to respective ones of the electrode segments. Each RF power supply subsystem includes a phase shifter (224), an amplifier/power supply (230), a circulator (236), a directional coupler (242), and a match network (MN/L). The latter has a match network impedance. The system further includes a control system (184) electronically connected to each RF power supply subsystem.Type: ApplicationFiled: September 17, 2002Publication date: March 20, 2003Inventor: Richard Parsons
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Patent number: 6535785Abstract: A system and method for monitoring the conditions in a gas plasma processing system while varying or modulating the RF power supplied to the system, so that resulting signals of the electrical circuits of the system provide information regarding operational parameters of the system or the state of a process. Significant improvements in sensitivity and accuracy over conventional techniques are thereby achieved. In addition, the plasma processing system can be thoroughly tested and characterized before delivery, to allow more accurate monitoring of and greater control over a process, thereby improving quality control/assurance of substrates being produced by the system. The information obtained by the modulation technique can be displayed on a monitor screen, in order to allow an operator to accurately monitor the system/process and diagnose any problems with the system/process.Type: GrantFiled: October 31, 2001Date of Patent: March 18, 2003Assignee: Tokyo Electron LimitedInventors: Wayne Johnson, Richard Parsons
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Patent number: 6531069Abstract: RIE processing chambers includes arrangements of gas outlets which force gas-flow-shadow elimination. Means are provided to control and adjust the direction of gases to the outlet to modify and control the direction of plasma flow at the wafer surface during processing. Means are provided to either move the exhaust paths for exhaust gases or to open and close exhaust paths sequentially, in a controlled manner, to modify flow directions of ions in the etching plasma. A combination of rotation/oscillation of a magnetic field imposed on the RIE chamber can be employed by rotation of permanent magnetic dipoles about the periphery of the RIE chamber or by controlling current through a coil wrapped around the periphery of the RIE process chamber to enhance the removal of the residues attributable to gas-flow-shadows formed by linear ion paths in the plasma.Type: GrantFiled: June 22, 2000Date of Patent: March 11, 2003Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Peter C. Wade, William H. Brearley, Jonathan H. Griffith
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Publication number: 20030022401Abstract: In the present invention, a device for inspecting semiconductor devices, which inspects intricate circuit patterns using images formed by the irradiation of white light, a laser light, or an electron beam, is equipped with a function that enables automatic setting of a plurality of parameters in the inspection device by using semiconductor device design data. This helps to improve the operation efficiency of inspection when the conditions required for inspection are set.Type: ApplicationFiled: February 22, 2002Publication date: January 30, 2003Applicant: Hitachi, Ltd.Inventors: Akira Hamamatsu, Minori Noguchi, Yoshimasa Ohshima, Hidetoshi Nishiyama
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Publication number: 20030019840Abstract: The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber.Type: ApplicationFiled: March 27, 2002Publication date: January 30, 2003Inventors: Michael Lane Smith, Pamela Denise Peardon Ward, Joel O?apos;Don Stevenson
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Publication number: 20030019839Abstract: For maintenance after wet cleaning of a plasma processing apparatus which processes a specimen in a vacuum processing chamber by using a plasma, when restoration processing after the wet cleaning of members configuring the vacuum processing chamber is performed with the vacuum processing chamber opened to the atmosphere, it is automatically or semiautomatically judged whether the restoration processing is appropriate or not according to a predetermined optimum sequence inherent in the apparatus, and the next processing is started automatically or semiautomatically according to the results.Type: ApplicationFiled: September 6, 2001Publication date: January 30, 2003Inventors: Hideyuki Yamamoto, Toshio Masuda, Shoji Ikuhara, Akira Kagoshima, Junichi Tanaka
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Publication number: 20030000922Abstract: A system for characterizing an etch process via scatterometry based real time imaging is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time etch image to characterize the progress of the etching and, in one example, produces suggested adaptations to the etch process.Type: ApplicationFiled: June 27, 2001Publication date: January 2, 2003Inventors: Ramkumar Subramanian, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton
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Publication number: 20020197747Abstract: An organic film is etched by using plasma generated from an etching gas including a first gas containing, as a principal constituent, a compound including carbon, hydrogen and nitrogen and a second gas including a nitrogen component.Type: ApplicationFiled: August 9, 2002Publication date: December 26, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD.Inventors: Hideo Nakagawa, Toshio Hayashi, Yasuhiro Morikawa
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Patent number: 6498045Abstract: A method for detecting an end point of an etching step conducted in an etching chamber. A target emission intensity level is selected for the etching step, and the etching step is performed in the etching chamber. A raw emission intensity level is sensed from the etching chamber during the etching step with an emission intensity level detector. The raw emission intensity level sensed from the etching chamber by the emission detector is modified with an emission intensity level modifier. The raw emission intensity level sensed with the emission intensity level detector from the etching chamber during the etching step is adjusted to the target emission intensity level by adjusting the emission intensity level modifier. The etching process is stopped upon occurrence of a predetermined spectral event sensed by the emission intensity level detector.Type: GrantFiled: June 11, 2001Date of Patent: December 24, 2002Assignee: LSI Logic CorporationInventor: Shiqun Gu
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Publication number: 20020192845Abstract: A method of forming an optical marker layer for etch endpoint determination in integrated circuit fabrication processes is disclosed. The optical marker layer is used in conjunction with organic and/or carbon-containing material layers that are used as bulk insulating materials and barrier materials. The optical marker layer is formed on the bulk insulating material layer and/or the barrier material layer by incorporating an optical marker into the surface thereof. The optical marker is incorporated into the surface of the bulk insulating material layer and/or the barrier material layer by treating such layer with an optical marker-containing gas. The optical marker layer provides an optical marker emission spectrum when it is etched during a subsequent patterning step.Type: ApplicationFiled: June 14, 2001Publication date: December 19, 2002Inventors: Huong Thanh Nguyen, Yunsang Kim, Ellie Yieh, Li-Qun Xia
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Patent number: 6496959Abstract: A system for estimating a plasma damage for subsequent layout design of a semiconductor device includes an antenna ratio extraction unit for extracting an antenna ratio from each of existing provisional layout patterns to be exposed to plasma in each of plasma processes. An index calculation unit is connected to the antenna ratio extraction unit for receiving the antenna ratio extracted by the antenna ratio extraction unit and calculating an individual damage index representing a degree of a plasma damage in accordance with the antenna ratio. An index addition unit is connected to the index calculation unit for receiving the individual damage indexes from the index calculation unit and adding the individual damage indexes to estimate a plasma damage.Type: GrantFiled: July 14, 2000Date of Patent: December 17, 2002Assignee: NEC CorporationInventor: Ko Noguchi
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Patent number: 6492186Abstract: A method for determining an endpoint for an oxygen free plasma stripping process for use in semiconductor wafer processing. The method comprises exciting a gas composition containing a nitrogen gas and a reactive gas to form the oxygen free plasma. The oxygen free plasma reacts with a substrate having a photoresist and/or residues thereon to produce emitted light signals corresponding to an oxygen free reaction product. The endpoint is determined by optically measuring a primary emission signal of the oxygen free reaction product at a wavelength of about 387 nm. The endpoint is determined when the plasma no longer reacts with the photoresist and/or residues on the substrate to produce the emitted light at about 387 nm, an indication that the photoresist and/or residues have been removed from the wafer. Secondary emission signals of the oxygen free reaction product at about 358 nm and 431 nm can also be monitored for determining the endpoint.Type: GrantFiled: November 5, 1999Date of Patent: December 10, 2002Assignee: Eaton CorporationInventors: Qingyan Han, Palani Sakthivel, Ricky Ruffin, Andre Cardoso