Plasma Etching Patents (Class 438/9)
  • Patent number: 6210593
    Abstract: In etching a target film to be etched antecedently, an etching rate is measured at each of the peripheral and central portions of the target film. If the etching rate is higher at the peripheral portion of the target film to be etched antecedently than at the central portion thereof, a focus ring positioned around a wafer is moved upward in etching a target film to be etched subsequently, so that the quantity of radicals arriving at the peripheral portion of the target film to be etched subsequently is decreased. If the etching rate is lower at the peripheral portion of the target film to be etched antecedently than at the central portion thereof, the focus ring is moved downward in etching the target film to be etched subsequently, so that the quantity of radicals arriving at the peripheral portion of the target film to be etched subsequently is increased.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: April 3, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Ohkuni, Masafumi Kubota
  • Patent number: 6200822
    Abstract: A method for detecting the transition between different materials in semiconductor structures during alternating etching and covering steps for anisotropic depthwise etching of defined patterns performed using a plasma. Provision is made for ascertaining, by way of an intensity measurement of at least one specific substance contained in the plasma, the beginning of each etching step by the fact that a characteristic threshold is reached, this also being achievable by way of an external synchronization signal which indicates the beginning and end of each etching step; for then, when the threshold value is reached, starting a delay time which is longer than the course of a first concentration maximum; for a second concentration maximum then to be ascertained after the delay time has elapsed; and for the second concentration maxima of the etching steps to be monitored as to whether they exceed or fall below the predefined value, in order to detect a material transition.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: March 13, 2001
    Assignee: Robert Bosch GmbH
    Inventors: Volker Becker, Franz Laermer, Andrea Schilp
  • Patent number: 6200908
    Abstract: A process for reducing the waviness of a semiconductor wafer utilizing plasma assisted chemical etching is disclosed. The process includes measuring the surface profile at discrete points on one surface of the wafer independent from the apposing surface, computing a dwell time versus position map based on the measured surface profiles, and selectively removing material from each surface of the wafer by plasma assisted chemical etching to reduce the waviness of the wafer.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: March 13, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Roland Vandamme, Ankur Desai, Dale Witte, Yun-Biao Xin
  • Patent number: 6192826
    Abstract: The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: February 27, 2001
    Assignee: Sandia Corporation
    Inventors: Michael Lane Smith, Jr., Joel O'Don Stevenson, Pamela Peardon Denise Ward
  • Patent number: 6187685
    Abstract: There is disclosed a method and apparatus for etching a substrate. The method comprises the steps of etching a substrate or alternately etching and depositing a passivation layer. A bias frequency, which may be pulsed, may be applied to the substrate and may be at or below the ion plasma frequency.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: February 13, 2001
    Assignee: Surface Technology Systems Limited
    Inventors: Janet Hopkins, Ian Ronald Johnston, Jyoti Kiron Bhardwaj, Huma Ashraf, Alan Michael Hynes, Leslie Michael Lea
  • Patent number: 6171973
    Abstract: A process for etching a gate conductor material in the fabrication of MOS transistors is presented. A hard mask layer composed of silicon oxynitride is formed upon a gate conductor layer. The hard mask layer is preferably patterned using a resin layer. The patterned hard mask layer is preferably used to form a patterned gate conductor. The gate conductor is preferably composed of polycrystalline silicon or a silicon-germanium alloy.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: January 9, 2001
    Assignee: France Telecom
    Inventors: Patrick Schiavone, Fr{acute over (e)}d{acute over (e)}ric Gaillard
  • Patent number: 6165312
    Abstract: The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: December 26, 2000
    Assignee: Sandia Corporation
    Inventors: Michael Lane Smith, Jr., Joel O'Don Stevenson, Pamela Peardon Denise Ward
  • Patent number: 6159864
    Abstract: The present invention provides a method for preventing gate oxides on a semiconductor wafer from being damaged by electromagnetic waves or particles generated in a plasma-related process. The semiconductor wafer comprises a substrate, a plurality of gate oxides positioned separately on the substrate, a first dielectric layer positioned on the gate oxides for isolating the gate oxides, and a conducting layer positioned on the first dielectric layer having at least one testing slit with a predetermined test pattern installed above each of the gate oxides. The method first performs a predetermined plasma-related process on the surface of the semiconductor wafer. Next, an electrical test is performed to find damaged gate oxides out of the gate oxides on the substrate. Based on damages of the damaged gate oxides, the predetermined plasma-related process is adjusted to prevent gate oxides on other semiconductor wafers from being damaged in the predetermined plasma-related process.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: December 12, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Mu-Chun Wang, Shih-Chung Li, Shih-Chieh Kao
  • Patent number: 6157447
    Abstract: The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: December 5, 2000
    Assignee: Sandia Corporation
    Inventors: Michael Lane Smith, Jr., Joel O'Don Stevenson, Pamela Peardon Denise Ward
  • Patent number: 6153115
    Abstract: Plasma process analysis techniques are provided. The intensity of each of a number, P, of a plurality of radiation wavelengths that are emitted from a plasma process are monitored as the process proceeds. Indications of P-dimensional correlations between the intensities of the P monitored wavelengths are produced as the process proceeds. Then the produced correlation indications are compared with a prespecified correlation indication generated based on historical conditions for the plasma process, to determine the status condition of the process as the process proceeds. With this technique, the use of a priori, expected, specific templates is not required for evaluating radiation emission data during a plasma process. Instead the techniques investigate and discover the multiple complex correlations that form between various radiation emission wavelengths during a plasma process, and do not impose an expectation for a specific correlation or trend between the various wavelengths.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: November 28, 2000
    Assignee: Massachusetts Institute of Technology
    Inventors: Minh Le, Kuang Han Chen, Taber H. Smith, Duane S. Boning, Herbert H. Sawin
  • Patent number: 6127271
    Abstract: A process for dry etching a surface within a vacuum treatment reactor includes evacuating the reactor, generating a glow discharge within said reactor, feeding a reactive etching gas into said reactor and reacting said etching gas within said reactor, removing gas with reaction products of said reacting from said reactor and installing an initial flow of said etching gas into said reactor and reducing said flow after a predetermined time span and during said reacting. The vacuum treatment reactor has a reactor with a pumping arrangement for evacuating the reactor. A glow discharge generating arrangement is connected to an electric power supply. A gas tank arrangement is connected to the reactor and has a reactive etching gas such as SF.sub.4.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: October 3, 2000
    Assignee: Balzers Hochvakuum AG
    Inventors: Emmanuel Turlot, Jacques Schmitt, Philippe Grousset
  • Patent number: 6096232
    Abstract: A dry etching system capable of suppressing the effect of reaction products generated in a reaction chamber during an etching process to the edge profile of an etch object such as a semiconductor wafer. This system includes a reaction chamber in which an etching action is performed, a plasma generator for generating plasma in the reaction chamber, a holder for holding an etch object in the reaction chamber, a detector for detecting the quantity of a reaction product contained in the plasma, and a controller for controlling the amount of the reaction products contained in the plasma to be at least one specific value. The etch object is etched by the action of etching species contained in the plasma. The detector detects, for example, the intensity of light emission from the plasma at a specific wavelength.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventor: Toshiki Hashimoto
  • Patent number: 6077387
    Abstract: Method and system for monitoring a plasma etch process performed in a plasma processing chamber, the method and system being capable of accurately monitoring and controlling the plasma etch process without being affected by the change in a plasma light emission transmission characteristically caused by process polymer depositions on a detecting surface or sampling window.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: June 20, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Mark R. Tesauro
  • Patent number: 6068783
    Abstract: A spectroscopic method is disclosed to provide a non-intrusive and in-situ monitoring of plasma etching conditions during the fabrication of semiconductor devices using RF power. It includes the steps of: (a) selecting a single plasma gas as a probe, in a cleaned plasma etch chamber; (b) measuring the spectral intensities of the plasma gas; and (c) plotting the measured spectral intensities either directly or indirectly against the RF time. A single plasma gas is selected which exhibits opposite relationships with RF time at two respective wavelengths.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: May 30, 2000
    Assignee: Winbond Electronics Corp
    Inventor: Steven Lee Szetsen
  • Patent number: 6060328
    Abstract: An arrangement is provided for collecting, measuring and analyzing at least two specific wavelengths of optical emissions produced while etching a semiconductor wafer in a plasma chamber to determine an optimal endpoint for the etching process. The arrangement includes a sensor for gathering optical emissions, an interface for converting the intensity of optical emissions into corresponding electrical signals, and a controller for determining an optimal endpoint based on the corresponding electrical signals for the two specific wavelengths and other predetermined threshold data.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: May 9, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William G. En, Allison Holbrook, Fei Wang
  • Patent number: 6060329
    Abstract: A method for plasma treatment is disclosed which effects detection of the amount of particles in an plasma generation area measuring the electron density in the particles based on the numerical value of the electric density in the plasma generation area.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: May 9, 2000
    Assignee: Fujitsu Limited
    Inventors: Takeshi Kamata, Hiroshi Arimoto
  • Patent number: 6057247
    Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: forming an oxide film on a substrate having a silicon region at least on the surface thereof; defining a resist pattern on the oxide film; placing the substrate on an electrode provided inside a reaction chamber of a plasma etching apparatus, and etching the oxide film by using plasma generated from a gas including a fluorocarbon gas with a bias voltage applied to the substrate; and removing fluorine from the reaction chamber by generating oxygen plasma inside the reaction chamber with substantially no bias voltage applied to the substrate.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: May 2, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Shinichi Imai, Nobuhiro Jiwari
  • Patent number: 6054333
    Abstract: A method is provided for determining etching characteristics during gas phase etching of thin film materials such as semiconductors during manufacture of devices. Etch end point, rate of etching, uniformity of etching and uniformity of growth of thin films can be determined. Isotopically enriched materials are deposited in layers which may be only a few nanometers thick at selected locations during growth of the thin films. The isotopes are removed during gas phase etching, carried by gas into an analysis chamber, condensed on a surface, and analyzed for isotopical composition. Mass spectroscopy of recoiled ions is a preferred detection technique.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: April 25, 2000
    Assignee: University of Houston
    Inventor: Abdelhak Bensaoula
  • Patent number: 6028008
    Abstract: The invention relates to calibration standards which are used chiefly for the calibration of profilometers and in atomic force- and scanning probe microscopes. The calibration standard has one step of defined height H or a multi-step system formed of several steps of the same step-height H and consisting of exactly one material. The manufacturing procedure for the calibration standard requires only a single masking layer for each of the different versions in the form of a one-step standard or a multi-step system.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: February 22, 2000
    Assignee: International Business Machines Corporation
    Inventors: Thomas Bayer, Johann Greschner, Klaus Meissner
  • Patent number: 5989929
    Abstract: A reactor is composed of a lower frame of a chamber, a quartz dome, an upper electrode, an 0 ring, and the like. A lower electrode and a substrate as a workpiece to be processed thereon are disposed in the reactor. The temperature of the quartz dome is maintained at a temperature of 180.degree. C. or higher by means of a heater. Fluorocarbon gas such as C.sub.2 F.sub.6 gas or C.sub.4 F.sub.8 gas is introduced into the reactor through a gas inlet and RF power from a first RF power source is applied to an antenna coil to produce a plasma and thereby etch an oxide film on the substrate. By heating the quartz dome to a high temperature, a deposit which hinders the release of oxygen from a wall face is prevented from being attached and the deposit on the bottom of the hole which causes an etch stop during processing is removed with oxygen. This prevents the etch stop during an etching process for forming a deep hole.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: November 23, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Hideo Nikoh, Shinichi Imai, Nobuhiro Jiwari, Satoshi Nakagawa, Shoji Matsumoto, Yoji Bito
  • Patent number: 5989928
    Abstract: In order to detect the end point of a plasma process stably and at a high precision always without being affected by the fine delineation of a pattern to be processed and an external disturbance, it is constructed such that emission wavelength components 27 of species are taken out of a plasma emission 24 and only a frequency component synchronous with a high-frequency electric power for plasma excitation is extracted by a synchronous detection circuit 30 and so on. Thereby, the progressing status of etching is seized more accurately and a change in signal at an end point becomes clear. As a result, the precision of detection of the end point of a plasma process for a minute aperture pattern is improved.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: November 23, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiko Nakata, Takanori Ninomiya
  • Patent number: 5980767
    Abstract: Disclosed herein is a method of detecting an end point of plasma process performed on an object, and a plasma process apparatus. The method includes the steps of detecting an emission spectrum over a wavelength region specific to C.sub.2 in the plasma, by optical detecting means, and determining the end point of the plasma process from the emission intensity of the emission spectrum detected by the optical detector. The apparatus has a process chamber, a pair of electrodes, a light-collecting device, an optical detector, and a determining device. The chamber has a monitor window. The electrodes are located in the process chamber. The first electrode is used to support the object. A high-frequency power is supplied between the electrodes to change a process gas into plasma. The light-collecting device collects the light from the plasma through the monitor window. The optical detector detects an emission spectrum from the light collected.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: November 9, 1999
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Chishio Koshimizu, Kimihiro Higuchi
  • Patent number: 5980766
    Abstract: A method of designing a reactor 10. The present reactor design method includes steps of providing a first plasma etching apparatus 10 having a substrate 21 therein. The substrate includes a top surface and a film overlying the top surface, and the film having a top film surface. The present reactor design method also includes chemical etching the top film surface to define a profile 27 on the film, and defining etch rate data from the profile region. A step of extracting a reaction rate constant from the etch rate data, and a step of using the reaction rate constant in designing a second plasma etching apparatus is also included.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: November 9, 1999
    Assignee: Daniel L. Flamm
    Inventors: Daniel L. Flamm, John P. Verboncoeur
  • Patent number: 5966586
    Abstract: Methods for determining an endpoint for a plasma etching process. The plasma etching process is employed to etch a substrate in a plasma processing chamber. The method includes detecting, using a mass analyzer, a density of a predefined compound in the plasma processing chamber. The method further includes outputting from the mass analyzer a variable signal responsive to the detecting. There is also included producing, responsive to the variable signal, a control signal. The control signal is outputted when a predefined density criteria is detected in the variable signal. Additionally, there is included initiating an etch termination procedure, responsive to the control signal, thereby ending the plasma etching process at an end of the etch termination procedure.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: October 12, 1999
    Assignee: Lam Research Corporation
    Inventor: Fangli Hao
  • Patent number: 5960254
    Abstract: An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: September 28, 1999
    Assignee: International Business Machines Corporation
    Inventor: John Edward Cronin
  • Patent number: 5956564
    Abstract: An apparatus in accordance with this invention includes an alignment mark that is formed in a substrate. The alignment mark extends across a dice line so that, upon dicing the substrate, the mark is exposed in the substrate's side edge. The mark is formed at a predetermined distance from a position at which a feature is desired to be formed on the substrate's side edge using a mask. Accordingly, the mark is a positional reference that can be used for highly accurate placement of the feature on the side surface of the substrate with the mask. Preferably, the mark is formed of metal or other material enhanced to a size that is readily detectable by an alignment system with which the mark is to be used. The invention also includes methods for making the alignment mark.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: September 21, 1999
    Assignee: Ultratech Stepper, Inc.
    Inventors: Thomas H Newman, Norbert Kappel
  • Patent number: 5953578
    Abstract: A semiconductor wafer is planarized by first mapping the flatness profile and then etching the wafer according to the flatness profile. Mapping is accomplished by scanning the wafer with a light beam. The flatness information is obtained by a phase detector comparing the phase of the reflected light beam and a reference light, and is then stored in a memory. The etching is implemented with scanning chemical ion beam etching, in which a reactive gas etches the wafer from spot to spot according to the instantaneous volume of reacting gas or the potential at the wafer, and is controlled by the data stored in the memory. The method can be used to planarize both semiconductor and metal.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: September 14, 1999
    Assignee: Winbond Electronics Corp.
    Inventor: William Wei-Yen Lee
  • Patent number: 5930585
    Abstract: In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. The storage capacitor is formed in a trench etch in a silicon substrate which is partially filled with polysilicon. The substrate is conformally coated by a TEOS SiO.sub.2 collar layer having a non-uniform thickness. A chemistry having a high TEOS SiO.sub.2 /Si3N.sub.4 and polysilicon selectively (i.e. which etches TEOS SiO.sub.2 faster than Si.sub.3 N.sub.4 and polysilicon by a factor of at least 6) is used to anisotropically etch the collar layer. C.sub.4 F.sub.8 /Ar/C) mixtures which have selectivities of 9:1 and 15:1 are adequate. When the surface of the Si.sub.3 N.sub.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Phillipe Coronel, Renzo Maccagnan
  • Patent number: 5925575
    Abstract: A process for forming a planarized, insulator, or silicon oxide filled shallow trench has been developed. The process features a hybrid planarization procedure, comprised of an initial dry etching cycle, used to remove all but about 100 to 500 Angstroms of silicon oxide, from subsequent device regions, or regions outside the insulator filled trench. Silicon oxide residing on the insulator filled trench is protected by a photoresist shape. A final chemical mechanical polishing procedure is than employed to remove both the silicon oxide, on the insulator filled shallow trench, as well as removing the remaining silicon oxide on silicon nitride, in subsequent device regions. An endpoint monitoring procedure allows the detection of the remaining 100 to 500 Angstroms of silicon oxide, on silicon nitride.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: July 20, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hun-Jan Tao, Chia-Shiung Tsai
  • Patent number: 5897378
    Abstract: In the process of dry etching or the like, the bond between specific atoms contained in a deposit attached on the interior wall of a chamber and composed of an etching by-product is monitored by using an infrared ray. An incoming infrared ray generated from a light source for monitoring is directed to the deposit so that the absorption spectrum of an outgoing infrared ray passing through the deposit is measured by an infrared-ray measuring device. As a result, accurate information on the inside of the chamber can be obtained and a reduction in production yield due to variations in etching characteristics and generated particles can be prevented. Moreover, the availability of an apparatus can be increased by optimizing a maintenance cycle based on a specific variation in the absorption spectrum of the infrared ray. In particular, process administration and process control in such processing using plasma as dry etching and plasma CVD can be improved.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: April 27, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Koji Eriguchi
  • Patent number: 5885472
    Abstract: A method for detecting an etching endpoint and a plasma etching apparatus and a plasma etching system using such a device are disclosed, in which time series data of a signal corresponding to the amount of light of the plasma light generated during the plasma etching process are arithmetically processed, so that the change of light amount is corrected and an etching endpoint is detected from the time series data after the correction.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: March 23, 1999
    Assignee: Sumitomo Metal Industries Limited
    Inventors: Toshiya Miyazaki, Toshihiro Hayami, Tadao Nakatsuka, Hiroyuki Tanaka, Toshiyuki Nakamura
  • Patent number: 5877032
    Abstract: The present invention is directed to a process for device fabrication in which a pattern is transferred from a photoresist mask into an underlying layer of silicon dioxide. A plasma containing a fluorocarbon gas is used to etch the pattern into the underlying silicon dioxide layer. The plasma is monitored using optical emission spectroscopy to effect control of the etch process. The optical emission is monitored at select wavelengths. To control the process based on an observation of photoresist etch rate, two wavelengths are monitored. One is associated with a species that is produced by the interaction between the photoresist and the plasma, and one is associated with a species related to the plasma intensity.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: March 2, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Keith V. Guinn, Susan Clardy McNevin
  • Patent number: 5874318
    Abstract: According to the preferred embodiment, an erosion and dishing monitor and monitor method are provided that facilitates the accurate optimization of a planarization process as in semiconductor process. The dishing monitor comprises at least two monitor structure sets embedded in a semiconductor substrate, the monitor structure sets comprising a plurality of monitor structures connected together with a plurality of connective conductors. The erosion monitor comprises a plurality of elongated conductors embedded into a semiconductor substrate, the plurality of conductors having varying conductor widths and adjacent substrate widths.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: February 23, 1999
    Assignee: Internatioal Business Machines Corporation
    Inventors: Faye Diann Baker, Daniel Shaw Brooks, Robert Kenneth Leidy, Anne Elizabeth McGuire, Rock Nadeau
  • Patent number: 5871658
    Abstract: A method for monitoring and controlling a plasma etch method for forming a patterned layer. There is first provided a substrate having a blanket layer formed thereover, the blanket layer having a patterned photoresist layer formed thereupon. There is then etched through a plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer the blanket layer to form a patterned layer. The plasma etch method is monitored through an optical emission spectroscopy (OES) method which monitors a minimum of a first plasma etchant component which relates to a chemical etching of the blanket layer and a second plasma etchant component which relates to a physical sputter etching of the blanket layer and the patterned photoresist layer.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: February 16, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hun-Jan Tao, Chia Shiung Tsai, Chen-Hua Yu
  • Patent number: 5851925
    Abstract: A method for staining a wafer containing a semiconductor device is disclosed which properly delineates the various layers of the semiconductor device and provides good contrast for proper testing and diagnosis of problems using a scanning electron microscope. After grinding, lapping and polishing a surface of the semiconductor device, the surface is ion beam etched, reactive ion etched and stained. The staining solution is made from 1 part by volume hydrofluoric acid, 3 parts by volume nitric acid, and 6 parts by volume acetic acid. The staining solution is cooled and subjected to a light to slow the reaction of the staining solution with the semiconductor device. This prevents structure collapse and under or over etching, and provides an easily controllable staining process.
    Type: Grant
    Filed: July 2, 1996
    Date of Patent: December 22, 1998
    Inventors: Michelle Beh, Donald Grant
  • Patent number: 5851842
    Abstract: The measurement system comprises a holder for holding a dielectric film formed on at least a semiconductive substrate and sandwiched between the substrate and a conductive film, voltage application terminals for applying voltage between the substrate and the conductive film, variable voltage source for supplying the voltage to the voltage application terminals, a light source for irradiating the dielectric film with light including wavelength of an infrared region and transmitting the light through the dielectric film, light absorbance detector receiving the light transmitted through the dielectric film, for detecting absorbance of an absorbed light component in an absorption wavelength region intrinsic to the dielectric film, and a potential difference measurement unit for measuring a potential difference between the substrate and the conductive film of the dielectric film on the basis of change in absorbance of the light component when the voltage is changed by the variable voltage source.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: December 22, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Nobuo Hayasaka, Naoki Yasuda, Hideshi Miyajima, Iwao Higashikawa, Masaki Hotta
  • Patent number: 5824606
    Abstract: A method in a plasma processing system for modifying a phase difference between a first radio frequency (RF) signal and a second RF signal. The first RF signal is supplied by a first RF power source to a first electrode and the second RF signal is supplied by a second RF power source to a second electrode of a plasma processing system. The second RF power source is coupled to the first RF power source as a slave RF power source in a master-and-slave configuration. The method includes the step of ascertaining a phase difference between a phase of the first RF signal and a phase of the second RF signal. The method further includes the step of comparing the phase difference with a phase control set point signal to output a control signal to the second RF power source, whereby the second RF power source, responsive to the control signal, modifies the phase of the second RF signal to cause the phase difference to approximate a phase difference value represented by the phase control set point signal.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: October 20, 1998
    Assignee: Lam Research Corporation
    Inventors: Robert D. Dible, Stephen G. Bradley, Seyed Jafar Jafarian-Tehrani
  • Patent number: 5807761
    Abstract: In the manufacturing of 16 Mbit DRAM chips, the deep trench formation process in a silicon wafer by plasma etching is a very critical step when the etching gas includes 0.sub.2. As a result, the monitoring of the trench formation process and thus the etch end point determination is quite difficult. The disclosed monitoring method is based on zero order interferometry. The wafer is placed in a plasma etcher and a plasma is created. A large area of the wafer is illuminated through a view port by a radiation of a specified wavelength at a normal angle of incidence. The reflected light is collected then applied to a spectrometer to generate a primary signal S of the interferometric type. Next, this signal is applied in parallel to two filters. A low-pass filter produces a first secondary signal S1 that contains data related to the deposition rate and the redeposited layer thickness. A band-pass filter produces a second secondary signal S2 that contains data related to the trench etch rate and depth.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: September 15, 1998
    Assignee: International Business Machines Corporation
    Inventors: Philippe Coronel, Jean Canteloup
  • Patent number: 5792673
    Abstract: On an insulating film covering a silicon substrate formed with desired circuit elements, a first Al wiring layer is formed and at the same time a test pattern is formed by using the same Al layer. The test pattern has a same thickness as the first Al wiring layer and has a shape with different line/space ratios at a plurality of positions. A coated film is formed over the wiring layer and test pattern, and etched back. During this etch-back, the border position between the coated film at the space area in the test pattern and the exposed insulating film is optically detected to judge the etching amount, in accordance with previously measured correlation data between the border position and an etching amount. Thus, discrimination can be done whether the etching amount is optimum or not. A method of manufacturing a semiconductor device is provided which can easily judge through optical non-destructive inspection whether the etching amount is optimum or not.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: August 11, 1998
    Assignee: Yamaha Corporation
    Inventor: Masahiko Nagura
  • Patent number: 5788869
    Abstract: A method of etching a dielectric layer to form a via to an underlying conductive layer is described. The method includes etching selected portions of the dielectric using a plasma containing an etchant and monitoring electromagnetic energy of plasma emission radiation from the species to determine a ratio of a pair of the species in the plasma that is used to indicate the onset of an etch stop phenomenon. Etching of the dielectric continues and additional dielectrics are processed through the plasma etching step while the ratio of species is less than a predetermined threshold value. The process is stopped and a plasma reactor is cleaned once the ratio of the etchants exceeds the threshold value. The method can be used to form vias between a pair of conductive layers.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: August 4, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Timothy J. Dalton, Ann C. Westerheim, Jamshed Hoshang Dubash, Marion Garver, Richard A. Bickford
  • Patent number: 5785797
    Abstract: A method of and an apparatus for monitoring etching by-products, capable of detecting and analyzing laser induced fluorescent light generated upon irradiating laser beams onto a by-product formed in the etching process. The method includes the steps of: selecting an excited electron level capable of being borne by molecules or radicals of the by-product; irradiating onto the by-product a laser beam with energy of a wavelength corresponding to the selected excited electron level; optionally exciting the molecules or radicals of the by-product by the irradiated laser beam, thereby forming a primary excited state of the by-product; detecting a laser induced fluorescent light emitted from the by-product during the transition of the by-product from the primary excited state to a secondary excited state which exhibits an energy level lower than the primary excited state; and analyzing the detected laser induced fluorescent light.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: July 28, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Chang Ju Choi
  • Patent number: 5781445
    Abstract: A test structure is described which indicates the occurrence of plasma damage resulting from back-end-of-line processing of integrated circuits. The structure consists of a MOSFET which is surrounded by a conductive shield grounded to the substrate silicon along its base perimeter. The walls of the shield are formed from the sundry levels of conductive layers applied during the integrated circuit interconnection metallization beginning with contact metallurgy which is connected to a diffusion within the substrate. This diffusion is formed within a trench in field oxide surrounding the MOSFET and is of the same conductive type as the substrate material. The top conductive plate of the test structure is formed from a selected metallization layer of the integrated circuit. By forming test structures with top conductive plates formed from two different metallization levels, the plasma damage incurred during the intervening processing steps can be uniquely determined.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: July 14, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ruey-Yun Shiue, Sung-Mu Hsu
  • Patent number: 5780315
    Abstract: An improved method for selecting etch endpoint when dry etching conductive material layers for use in semiconductor device circuits has been created. The more precise endpoint selection procedure produces metallization patterns which are free from residues (resulting from under-etching) and free from sidewall attack and/or pattern degradation (resulting from over-etching). The method avoids costly and time consuming pre-sorting of substrates according to product pattern density.
    Type: Grant
    Filed: March 13, 1997
    Date of Patent: July 14, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ying-Chen Chao, Ting-Hwang Lin
  • Patent number: 5747201
    Abstract: A method for irradiating a substrate such as a semiconductor substrate, coated with a photoresist, with light to measure variations in optical properties such as reflectivity, refractive index, transmittance, polarization, spectral transmittance, for determining an optimum photoresist coating condition, an optimum photoresist baking condition, an optimum developing condition or an optimum exposure energy quantity, and forming a photoresist pattern according to the optimum condition. A system for the exposure method, a controlling method of forming a photoresist film by use of the exposure method, and a system for the controlling method, are useful for stabilization of the formation or treatment of the photoresist film, and ensure less variations in the pattern size.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: May 5, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nakayama, Masataka Shiba, Susumu Komoriya
  • Patent number: 5739051
    Abstract: Method and device for detecting the end point of a plasma process, the method and device being capable of making it unnecessary to set a threshold every process or every processed object and also capable of correctly detecting the end point of the plasma process even if process conditions are changed. The method and device can be therefore used for more purposes. According to the end point detecting method realized by the end point detecting device, the emission spectrum of an active species having a specific wavelength and caused when a semiconductor wafer W is processed with plasma P is detected by a photodetector and the end point of the plasma process is detected on the basis of light strength changes of the emission spectrum. More specifically, an average value m and dispersed ones .sigma..sup.2 of light strengths I are calculated for a predetermined time period T.sub.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: April 14, 1998
    Assignee: Tokyo Electron Limited
    Inventor: Susumu Saito
  • Patent number: 5658418
    Abstract: Detecting the desired etch end point in the dry etching of a structure that includes a dielectric film formed onto a substrate down to a given thickness Ef. The structure is placed in the chamber of an etching equipment provided with a view-port. A light source illuminates a portion of the structure at a normal angle of incidence through the view-port. The light contains at least two specified wavelengths (L1, L2) whose value is greater than a minimum value equal to 4*N*e (wherein N is the index of refraction and e the thickness error of the dielectric). The reflected light is applied to spectrometers tuned to each specified wavelength, for converting the reflected light into interference signals that are processed and analyzed in a dedicated unit to generate primary signals (S1, S2). An analysis of the primary signals is performed after a predetermined delay. For each wavelength, a pre-selected extremum of the primary signal is detected and a predetermined number of extrema is counted.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventors: Philippe Coronel, Jean Canteloup
  • Patent number: 5658423
    Abstract: A method of monitoring the status of plasma in a chamber using real-time spectral data while conducting an etch process during the course of manufacturing of semiconductor wafers. Spectral data is collected during etching, with the spectral data characterizing an emission of light from etch species contained in the plasma, and maintaining the collected data as reference data. A model of principal components of the data is generated. Additional spectral data is extracted from the plasma and compared with the model. Discrepancies pinpoint the presence of foreign material faults and help determine the cause of the failures to ensure appropriate corrective action.
    Type: Grant
    Filed: November 27, 1995
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventors: David Angell, Paul Bao-Luo Chou, Antonio Rogelio Lee, Martin Clarence Sturzenbecker
  • Patent number: 5654903
    Abstract: The present invention provides a method and apparatus for monitoring the state of an attribute of a product during the manufacturing process. The invention employs an intelligent system trained in the relationship between the signatures of the manufacturing process and the product attribute as a function of time. In one embodiment the intelligent system comprises two intelligent systems: the first, trained in the relationship between the signatures of the manufacturing process and one or more signatures of the state of the attribute as a function of time; and the second, trained in the relationship between the product-state signatures as a function of time and the product attribute as a function of time. The disclosed apparatus can be an integral part of the manufacturing machinery allowing the process to continue until the exact moment when the desired state is achieved.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: August 5, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Edward A. Reitman, Dale E. Ibbotson, Tseng-Chung Lee
  • Patent number: 5653894
    Abstract: The present invention is predicated upon the fact that a process signature from a plasma process used in fabricating integrated circuits contains information about phenomena which cause variations in the fabrication process such as age of the plasma reactor, densities of the wafers exposed to the plasma, chemistry of the plasma, and concentration of the remaining material. In accordance with the present invention, a method for using neural networks to determine plasma etch end-point times in an integrated circuit fabrication process is disclosed. The end-point time is based on in-situ monitoring of at least two parameters during the plasma etch process. After the neural network is trained to associate a certain condition or set of conditions with the endpoint of the process, the neural network is used to control the process.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: August 5, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Dale Edward Ibbotson, Tseng-Chung Lee, Helen Louise Maynard, Edward Alois Rietman
  • Patent number: 5635021
    Abstract: There is disclosed a dry etching method capable of achieving the formation of vertical line patterns and the minimization of a difference in size between an isolated line pattern and an inner line pattern. When the line width of an inner line pattern is smaller than that of an isolated line pattern and when the width of a line pattern is greater than the width of a resist pattern, at least one parameter selected from the parameter group consisting of the pressure of a raw-material gas mixture introduced into a vacuum chamber, the exhaust amount of gas discharged from the vacuum chamber, a high-frequency electric power, the frequency of the high-frequency electric power, the rate of a lateral wall protecting gas in the raw-material gas mixture and the temperature of a sample stand, is changed such that the amounts in which the line patterns are etched, are increased and that the amount in which the inner line pattern is etched, is smaller than the amount in which the isolated line pattern is etched.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: June 3, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenji Harafuji