Abstract: System and method for converting disk format types of virtual disks in storage executes, in response to a request to convert a disk format type of a target virtual disk from a source disk format type to a destination disk format type, a conversion procedure on each data block of the target virtual disk that satisfies a predefined condition. The conversion procedure executed is based on the source and destination disk format types. The conversion procedure includes taking possession of a granular offset lock for a data block of the target virtual disk, performing a conversion operation on the data block of the target virtual disk only when the data block of the target virtual disk satisfies a required condition, and releasing the granular offset lock for the data block of the target virtual disk after the conversion operation on the data block has been performed.

Abstract: A data path for memory addressable using an addressing scheme based on a minimum addressable unit, such as a byte, having a size (e.g. 8) which is a power of 2, is configured for transferring data between the memory array and a data interface using a transfer storage unit having N bits (e.g. 12), where N is an integer that is not a power of 2. A page buffer and cache in the data path can be configured in unit arrays with N rows, and to transfer data in the transfer storage units from selected N cell columns.

Abstract: Methods and systems implement a data recovery bypassing protocol, by which a storage node of a cloud network may return a replica of lost data being recovered to timely service a read operation call from a computing node of the cloud network, without waiting for completion of a first, a second, and a third recovery function. Storage devices implement asynchronous event reporting (“AER”) protocol between a storage engine and storage devices of the storage node. Within a storage device, an AER generation protocol enables a storage controller and a flash memory cell array of the storage device to intercommunicate, and enables the storage controller to generate AER messages. By bypassing secondary recovery, the computing node may successfully read lost data from many or all storage nodes of the cloud network, thus completing read operation calls without suffering milliseconds in performance loss and blocking, averting observable degradation of QoS of the overall computing system.

Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.

Abstract: An operation method of a storage device, which includes a nonvolatile memory device, includes receiving a first key-value (KV) command including a first key from an external host device; transmitting a first value corresponding to the first key from the nonvolatile memory device to the external host device as first user data, in response to the first KV command; receiving a second KV command including a second key, from the external host device; and performing a first administrative operation based on a second value corresponding to the second key, in response to the second KV command. The first KV command and the second KV command are KV commands of a same type.

Abstract: Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.

Abstract: File metadata structures of a file system are analyzed. At least one metadata element that is duplicated among the analyzed file metadata structures is identified. The at least one identified metadata element is deduplicated including by modifying at least one of the file metadata structures to reference a same instance of the identified metadata element that is referenced by another one of the file metadata structures.

Abstract: A FLASH controller includes a main control module; and an arbitration module, a read data fifo, and a write data fifo connected with the main control module. The read data fifo and the write data fifo are both connected with the arbitration module and a data interface module, and the data interface module is connected with an AHB data bus. The controller further includes a register module that is connected with the read data fifo, the write data fifo, the arbitration module, and a configuration interface module. The configuration interface module is connected with an AHB configuration bus, and the main control module is connected with the register module through a synchronization module. The AHB data bus interface and the AHB configuration bus interface are adopted for different operations, and general read-write operations of FLASH are realized through DMA data transfer and high-capacity internal cache units, improving data transfer efficiency.

Abstract: Systems and methods are disclosed comprising receiving L2P table information from a storage system over a communication interface, maintaining a host L2P table at a physical address using the received L2P table information, and providing a read command to the storage system for first data associated with a first LBA and a host L2P entry associated with the first data. The host L2P entry can include a physical address of the first LBA on the storage system according to the host L2P table and a physical address of a portion of the L2P table on the storage system associated with the first LBA. Control circuitry of the storage system can validate the physical address of the first LBA from the host L2P entry using the physical address of the portion of the host L2P table associated with the first LBA.

Abstract: A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

Abstract: A method for securing data by embedding the data in a data structure and utilizing a sensor device to detect transfer of the data structure. The data is embedded such that the data is only accessible by first executing an executable program. If the executable program determines that the device attempting to access the data (the accessing device) does not have permission to access the data, then the executable program destroys all or a portion of the data. If the data structure is transferred to another device, a sensor device positioned to detect the data structure when transferred will identify the data. If the sensor device determines that the data structure is not permitted to be transferred, then the sensor device destroys all or a portion of the data.

Abstract: Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

Abstract: Methods, systems, and devices for cleaning memory blocks using multiple types of write operations are described. A counter may be incremented each time a write command is received. In response to the counter reaching a threshold, the counter may be reset and a flag may be set. Each time a cleaning of a memory block is to take place, the flag may be checked. If the flag is set, the memory block may be cleaned using a second type of cleaning operation, such as one using a force write approach. Otherwise, the memory block may be cleaned using a first type of cleaning operation, such as one using a normal write approach. Once set, the flag may be reset after one or more memory blocks are cleaned using the second type of cleaning operation.

Abstract: Methods, systems, and devices related to host identification for a memory system are described. A memory system may receive an index value from a host system that is associated with an identification of the host system. The memory system may identify one or more operating parameter associated with the index value based on receiving the index value. The memory system controller may configure the memory system to utilize one or more operating parameters associated with the index value based on identifying the operating parameters. The memory system may output an indication to the host system that the operating parameters associated with the index value are configured to be utilized by the memory system.

Abstract: Power recovery for data storage devices with an efficient space trimming technology is shown. A controller scans a non-volatile memory according to a programming order, collects a sequence of trimming information flags, and interprets a sequence of storage information scanned from the non-volatile memory to identify logical addresses and trimming code. Based on the logical addresses, a host-to-device mapping (H2F) table is rebuilt. Based on the trimming code, information of medium-length trimming and information of long-length trimming are recognized from a storage area of the non-volatile memory. According to the trimming information for medium-length trimming, dummy mapping data is programmed to the H2F table. According to the trimming information for long-length trimming, a trimming bitmap (TBM) is rebuilt. Each bit in the TBM marks space trimming of a first length.

Abstract: A semiconductor memory apparatus includes a memory bank circuit and a bandwidth control circuit. The memory bank circuit stores normal data, an error correction code, and a meta information code. The bandwidth control circuit controls bandwidths of the error correction code and the meta information code based on bandwidth option information.

Abstract: This application discloses a data processing method and apparatus, an electronic device, and a storage medium. When execution is performed at an operation layer of a neural network model, based on a pre-stored buffer allocation relationship, a first address range for cyclic addressing is set for a first buffer corresponding to input data and a second address range for cyclic addressing is set for a second buffer corresponding to an output result. Subsequently, cyclic addressing can be performed in the first buffer based on the first address range for cyclic addressing, to read the input data for the operation layer; and cyclic addressing can be performed in the second buffer based on the second address range for cyclic addressing, to write the output result of the operation layer into the second buffer. In this way, efficiency of buffer utilization can be effectively improved, and further operation efficiency for the model is improved.

Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.

Abstract: Method and apparatus for enhancing performance of a storage device, such as a solid-state drive (SSD). In some embodiments, the storage device monitors a rate at which client I/O access commands are received from a client to transfer data with a non-volatile memory (NVM) of the storage device. A ratio of background access commands to the client I/O access commands is adjusted to maintain completion rates of the client I/O access commands at a predetermined level. The background access commands transfer data internally with the NVM to prepare the storage device to service the client I/O access commands, and can include internal reads and writes to carry out garbage collection and metadata map updates. The ratio may be adjusted by identifying a workload type subjected to the storage device by the client.

Abstract: A computer-implemented method according to one aspect includes receiving a request to perform a transaction in persistent memory; determining a correlation between volatile memory address locations in a volatile transaction cache and persistent memory locations in the persistent memory; performing the transaction within the volatile memory address locations of the volatile transaction cache; identifying modified volatile memory address locations in the volatile transaction cache that have been written during the transaction; logging, within the persistent memory, data within the modified volatile memory address locations; copying the data within the modified volatile memory address locations to corresponding persistent memory locations in the persistent memory, utilizing the determined correlation; and removing the logged data from the persistent memory, in response to determining that the copying has completed.

Abstract: Methods and systems for processing a command from a host to a storage device are disclosed. A first controller of the storage device receives a first command from the host via a first queue. The first queue is exposed to the host. The storage device generates a second command based on the first command, and submits the second command to a second controller of the storage device via a second queue. The second command and the second queue are unexposed to the host. The second controller obtains and processes the second command from the second queue, where the processing of the second command is for accessing non-volatile storage media of the storage device. Based on a status of the second command, the first controller transmits a signal to the host for indicating completion of the first command.

Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

Abstract: A PCIe architecture is disclosed incorporating a controller memory buffer (CMB). Write data is written to the CMB and is not read out for processing upon receiving a write command for the write data. The data is read out of the CMB and processed to obtain processed data upon receiving feedback from a NAND channel controller. The processed data may be written directly to the NAND channel controller or may be written to a light write buffer that is read by the NAND channel controller. The processed data may be written to a light write buffer functioning as a cut through buffer.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: receiving, by a host system, an indication that a storage capacity of a memory sub-system is affected by a failure, wherein the memory sub-system stores data of a storage structure and comprises memory cells storing multiple bits per cell; instructing, by the host system, the memory sub-system to operate at a reduced capacity, wherein the reduced capacity reduces the quantity of bits stored per memory cell; receiving, by the host system, an indication that the memory sub-system comprises data in excess of the reduced capacity; providing, by the host system, a storage location to the memory sub-system, wherein the storage location is external to the memory sub-system; and enabling the memory sub-system to store the data of the storage structure at the storage location.

Abstract: A method includes utilizing, while delivery of power from a main power supply to a memory sub-system is interrupted, a processing device of the memory subsystem to monitor a characteristic of the memory sub-system associated with data retention at a non-volatile memory component of the memory sub-system. The method further includes utilizing, while delivery of power from a main power supply to a memory sub-system is interrupted, a processing device of the memory subsystem to predict, based on the monitored characteristic, an impending data loss event for the non-volatile memory component.

Abstract: Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Abstract: Systems, methods, and devices are described for writing to a solid-state drive (SSD) that includes a non-volatile memory device, the volatile memory device includes first and second memory regions, the first memory region storing an address mapping table. A write request that includes a host logic block address (LBA) and data is received. A determination of whether the received LBA corresponds to the non-volatile memory device or the second memory region is made. In response to the received LBA corresponding to the non-volatile memory device, a physical address of the non-volatile memory device corresponding to the received LBA is determined based on the address mapping table and the included data is written to the determined physical address of the non-volatile memory device. In response to the received LBA corresponding to the second memory region, the included data is written to the second memory region based on the received LBA.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device that manages map data using a volatile memory device having a limited capacity may include a nonvolatile memory device, a memory controller, and the volatile memory device which includes a map chunk buffer, a map chunk status table, a journal buffer, and a meta slice buffer.

Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.

Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). The metadata are stored in combined (combo) pages in a non-volatile memory (NVM) each having first and second level map entries. The second level map entries provide a logical-to-physical address translation layer for user data blocks stored to the NVM, and the first level map entries describe the second level map entries in the combo page. A global map structure is accessed to identify a selected combo page in the NVM associated with a pending access command. The first and second level map entries are retrieved from the combo page, and the second level map entries are used to identify a target location for the transfer of user data blocks to or from the NVM.

Abstract: According to one embodiment, a key search circuit includes a hit determination circuit that determines whether a key search request hits a content stored in a search result buffer, and an update determination circuit that determines whether to update the content stored in the search result buffer. When the hit determination circuit determines that the key search request hits the search result buffer, the key search circuit outputs the search result stored in the search result buffer to an encryption/decryption circuit. When the update determination circuit determines to update the search result buffer, the key search circuit updates the content stored in the search result buffer with the key search request and a search result obtained from a range table.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system may include a first processor and a second processor. The first processor is configured to manage or process a main read count table including a plurality of first read count table entries each corresponding to one of a plurality of super memory blocks. The second processor is configured to manage or process, when an error occurs during an operation of reading data stored in one of the plurality of super memory blocks, a partial read count table including a read count table entry including information on a count of the read operation executed during a recovery operation for the error, and transmit an update message to the first processor for updating the main read count table based on the partial read count table.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory includes first and second memory areas. The controller is configured to, when receiving a write command from the host, determine a write method. The controller is configured to, when a first method is determined, write the data to the first memory area. The controller is configured to, when a second method is determined, write the data to the second memory area. The first method is a write method of writing the data to a physical address associated with the logical address designated in the write command. The second method is a write method of writing the data to a physical address designated by the controller.

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a signaling can be received that indicates a request from a controller to migrate valid data from a first data block to a second data block. For example, the first data block can be a data block of a plurality of memory cells configured as single-level-cell (SLC) memory. The second data block can be configured as multi-level-cell (MLC) memory. The data migration operation can include an error control operation that is performed using the memory component, the error control operation excluding transferring the data to the controller. The data can be migrated from the first data block configured as SLC memory to the second data block configured as MLC memory after the error control operation is performed using the memory component.

Abstract: A method includes maintaining respective episodic memory data for each of multiple actions; receiving a current observation characterizing a current state of an environment being interacted with by an agent; processing the current observation using an embedding neural network in accordance with current values of parameters of the embedding neural network to generate a current key embedding for the current observation; for each action of the plurality of actions: determining the p nearest key embeddings in the episodic memory data for the action to the current key embedding according to a distance measure, and determining a Q value for the action from the return estimates mapped to by the p nearest key embeddings in the episodic memory data for the action; and selecting, using the Q values for the actions, an action from the multiple actions as the action to be performed by the agent.

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Abstract: A risk assessment method based on data priority, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a query command from a host system; in response to the query command, performing a data health detection on a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores data with multiple data priorities; generating risk assessment information according to a detection result, wherein the risk assessment information reflects a health degree of data with different data priorities in the rewritable non-volatile memory modules by different risk levels; and transmitting the risk assessment information to the host system.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

Abstract: A storage system has volatile memory for use as a cache and can extend the available caching space by using a host memory buffer (HMB) in a host. However, because accesses to the HMB involve going through a host interface, there may be latencies in accessing the HMB, To reduce access latencies, the storage system views the volatile memory and the HMB as a two-level cache. In one use case, the storage system decides whether to store a logical-to-physical address table in the volatile memory or in the HMB based on a prediction of the likelihood that the table will be updated. If the likelihood for an update is above a threshold, the table is stored in the volatile memory, thereby eliminating the access latencies that would be encountered if the table needs to be updated and is stored in the HMB.

Abstract: Various implementations described herein relate to systems and methods for enabling a data lane for communicating messages for each of a plurality of regions of a non-volatile memory. Each of the plurality of regions includes a plurality of dies. The messages for each of the plurality of regions are communicated via the data lane.

Abstract: The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to generate a result indicative of whether a number of free memory blocks satisfies a reference after beginning of garbage collection for the memory device, selectively perform a journaling operation for a request based on the result, and program data, collected by the garbage collection, in the memory device.

Abstract: A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.

Abstract: Systems and methods for modifying a usage limit of a data storage device include a host interface; integrated circuit memory cells; and a processing device coupled to the host interface to provide commands with addresses to access the integrated circuit memory cells according to the address, and configured to execute firmware to perform: operations requested by commands received via the host interface; and updates to a usage limit of the data storage device.

Abstract: A data storage device coupled to a controller. The controller is configured to determine whether a request to perform a data transfer operation has been received and determine whether a request to perform a garbage collection operation is necessary during the data transfer operation. The controller generates an extended logical-to-physical table (L2P) including information for the data transfer operation in response to determining the request to perform the data transfer operation has been received and the request to perform the garbage collection operation is necessary, transmits the extended L2P table to one or more peer data storage devices, and performs the garbage collection operation after transmitting the extended L2P table to the one or more peer data storage devices.

Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

Abstract: Systems and methods of tracking page state changes are provided. An input/output is communicatively coupled to a host having a memory. The I/O device receives a command from the host to monitor page state changes in a region of the memory allocated to a process. The I/O device, bypassing a CPU of the host, modifies data stored in the region based on a request, for example, received from a client device via a computer network. The I/O device records the modification to a bitmap by setting a bit in the bitmap that corresponds to a location of the data in the memory. The I/O device transfers contents of the bitmap to the CPU, wherein the CPU completes the live migration by copying sections of the first region indicated by the bitmap to a second region of memory. In some implementations, the process can be a virtual machine, a user space application, or a container.