Abstract: A predictive method for scheduling of the operations is described. The predictive method utilizes data generated from computing an expected lifetime of the individual files or objects within the container. The expected lifetime of individual files or objects can be generated based on machine learning techniques. Operations such as garbage collection are scheduled at an epoch where computational efficiencies are realized for performing the operation.

Abstract: A storage device includes a memory and a memory controller which transmits a command to the memory. The memory includes at least one memory cell array, a memory temperature sensor which measures a temperature of the memory, and a control logic. The control logic outputs a busy signal in response to the command, receives the temperature of the memory from the memory temperature sensor in response to the command, and determines whether to perform a command operation according to the command on the memory cell array based on the received temperature of the memory.

Abstract: A data storage device may include a first memory apparatus including a plurality of data blocks having data classified in units of data blocks; a second memory apparatus in communication with the first memory apparatus to store data cached from the first memory apparatus; and a controller in communication with the first memory apparatus and the second memory apparatus. The controller is configured to perform a caching group based caching operation by controlling the first memory apparatus to cache data from the first memory apparatus to the second memory apparatus on a caching group basis. Each caching group includes a first data block requested for caching and one or more other data blocks having the same write count as a write count of the first data block.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

Abstract: A data storage apparatus may include a storage and a controller. The storage includes a plurality of planes each composed of a plurality of memory blocks, and is divided into a first region and a second region. An original of system data and a copy of the system data are stored in the first region. The controller is configured to perform a relief operation of moving the copy of the system data stored in a source memory block of the first region to a victim plane and switching the source memory block to a region replaceable with the second region.

Abstract: Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types. Each block of the set of blocks includes pages of memory of a physical memory device. A subset of the pages of the block is identified. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.

Abstract: A storage device includes first and second memory devices, and a memory controller. The first memory devices correspond to a main data area. The second memory devices correspond to a reserved area. The memory controller is coupled to the first and second memory devices through first and second channels. A number of first memory devices coupled to the memory controller through the first channel is equal to a number of first memory devices coupled to the memory controller through the second channel, and a number of second memory devices coupled to the memory controller through the first channel is different from a number of second memory devices coupled to the memory controller through the second channel. The memory controller selects a memory device on which a write operation is to be performed, based on a memory state of the first and second memory devices.

Abstract: Systems and methods for peer storage devices to share host control data are described. Storage devices may include a host interface configured to connect to a host system and a control bus interface to connect to a control bus. Peer storage devices may establish peer communication through the control bus interface to share host control data, such as access parameters for host resources allocated to peer storage devices. A storage device may access host resources using access parameters allocated to that device, receive peer access parameters from a peer storage device, and access host resources allocated to the peer storage device using the peer access parameters. For example, a storage device may use a peer host memory buffer to store buffer data prior to releasing the host memory buffer allocated to it.

Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.

Abstract: Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.

Abstract: A memory device in accordance with a described method of operation includes a read only memory (ROM) address controller and a suspend signal generator. The ROM address controller is configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and to suspend output of the plurality of operation ROM addresses in response to a suspend signal. The suspend signal generator is configured to generate the suspend signal that is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output. The suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored.

Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.

Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.

Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Abstract: A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.

Abstract: A memory system includes a memory device suitable for storing data and a controller suitable for determining an operation state of the memory device and carrying out garbage collection to the memory device in response to the operation state. The controller can ignore a first command entered from a host while performing the garbage collection.

Abstract: Embodiments of systems and methods for fast input/output (IO) on PCIE devices are described. Such methods include receiving an IO request from a user or application, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device, analyzing information from the IO request in an IO block analyzer to select one of a plurality of communication paths for communicating the data with the host system, defining a routing instruction in a transfer routing information transmitter in response to the selected communication path, communicating the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system routing the data from the peripheral device to either the processing device or the memory device according to the routing instruction with a data transfer router.

Abstract: A scheme for handling program errors is provided for a memory system which includes a memory device and a controller including firmware and a memory interface. The firmware issues commands for program operations to the memory interface. After detecting a failed program operation in a particular memory block, the firmware reroutes that program operation to a different location in a different memory block and takes further action to reduce the likelihood of a subsequent error occurring in the same memory block in which the failed program operation occurred.

Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory controller may include a storage area manager and a write operation controller. The storage area manager may allocate a plurality of memory devices to a first group and a second group in response to a storage area setting command. The write operation controller may control a group selected from the first group and the second group according to a type of a write request to store write data. At least one memory devices in the first group includes memory blocks storing n data bits. At least one memory devices in the second group includes memory blocks storing m data bits.

Abstract: A system includes a memory circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

Abstract: Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the Processor to communicate with the one or more DRAMs via a memory interface.

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.

Abstract: An apparatus comprises a processing device. The processing device is configured to persistently store metadata pages on a plurality of storage devices. The metadata pages are organized into buckets. The processing device is configured to access a given metadata page based at least in part on a bucket identifier where the given metadata page corresponds to a given logical volume. The bucket identifier comprises a first portion comprising an indication of a given bucket range that corresponds to the given logical volume and a second portion comprising an indication of an offset into the given bucket range that corresponds to a grouping of buckets that correspond to the given logical volume. The grouping of buckets corresponds to the given logical volume. The bucket identifier further comprises a third portion comprising an indication of an offset into the grouping of buckets that corresponds to the bucket comprising the given metadata page.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, information associated with a relationship between a physical layer block and a virtual logic block for RAID storage. The information associated with the relationship between the physical layer block and the virtual logic block may be written within the RAID storage. The physical layer block within the RAID storage may be rebuilt only when the physical layer block includes the information associated with the relationship between the physical layer block and the virtual logic block.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory; generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size; and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.

Abstract: A data storage device includes a nonvolatile memory including a plurality of memory blocks and page buffers for data input/output, the page buffers being electrically connected to the plurality of memory blocks, respectively, and a controller configured to, when a number of free memory blocks among the plurality of memory blocks is equal to or less than a predetermined threshold number, select, as a candidate source memory block group, memory blocks each having a number of valid pages equal to or less than a predetermined number within the nonvolatile memory, select, as a source memory block, a memory block having a minimum amount of time required to read valid data from the valid page within the candidate source memory block group and perform a garbage collection operation to the source memory block.

Abstract: A storage device is provided. The storage device includes a boot ROM stores a plurality of public keys and a boot ROM image, an OTP memory identifies a first public key among the plurality of public keys, a first memory including a first area the stores the plurality of public keys and a flash boot image different from the boot ROM image, and a second area that stores a first boot signature corresponding to the flash boot image, a second memory including a first firmware image including a first firmware signature, and a memory controller that receives a second firmware image including a second firmware signature and a second boot signature, receives a second public key among the plurality of public keys and the flash boot image based on the second firmware image being received, and write the second boot signature in the second area of the first memory.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: A data processing system according to one embodiment includes first and second data storage devices having a storage medium capable of permanently storing data; a data holding device having a storage medium capable of storing the data at a higher speed than the first and second data storage devices; and a controller that determines the type of data to be processed, and, in the case where the data to be processed is structured data, stores the data to be processed in the data holding device, then, collectively, in the first data storage device, and, in the case where the data to be processed is binary data, stores the data to be processed in the data holding device and in the second data storage device.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.

Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device performs operations in parallel on a plurality of memory blocks. The controller determines, in response to a read request on a plane including a target memory block among the plurality of memory blocks, whether to perform a process for a partial suspension on the operations based on suspension counts of the plurality of memory blocks. The controller controls, when performing a process for the partial suspension, the non-volatile memory device to suspend the operation being performed on the target memory block and to keep performing the operations being performed on other memory blocks among the plurality of memory blocks.

Abstract: A method, article of manufacture, and apparatus for managing data. In some embodiments, this includes determining a usage level of a file, wherein the file is stored in a first storage system, moving the file to a second storage system based on the determined usage level of the file updating location information in a catalog based on the movement of the file, and performing at least a portion of a query on the file after updating location information in the catalog.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.

Abstract: A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of corresponding first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post processor generates a first row key that includes validity signals satisfying the data integrity.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to receive host commands, such as write commands. Upon determining that a received plurality of write commands are sequential, but includes one or more write commands that are unaligned with a memory granularity of the memory device, the one or more write commands are revised such that the one or more write commands are aligned with the memory granularity. The revised write command includes a first of the one or more write commands and a portion of a second of the one or more write commands. A beginning of the revised write command is aligned with the memory granularity and the end of the revised write command is also aligned with the memory granularity.

Abstract: A technique for managing SSDs in a data storage system generates an endurance value for each of multiple SSDs and arranges the SSDs in RAID groups based at least in part on the generated endurance values. As a result of such arranging, some RAID groups may include only SSDs with higher endurance values while other RAID groups may include only SSDs with lower endurance values. The data storage system may then run RAID groups with higher endurance values at higher speeds and may run RAID groups with lower endurance values at lower speeds.

Abstract: An interface receives storage requests for storing data in a software-defined storage network using an append-only storage scheme. The requests include an identifier of a data object to be stored. The requests are agnostic of hardware-specific details of the storage devices. A virtualization layer accesses space allocation data for the storage devices; and policies for prioritizing performance. Based on the data and policies, a physical storage location at the plurality of storage devices is selected for storing the data object. Metadata is generated for the data object indicating that the data object is an append-only object and mapping the physical storage location of the data object to the identifier. The request is translated to instructions for storing the data object at the physical storage location using the append-only storage scheme. The data object is stored at the physical storage location using the append-only storage scheme.

Abstract: A method for provided use in a storage device having a controller, the method comprising: identifying, by the controller, a plurality of logical regions in the storage device; obtaining, by the controller, a respective usage metric for each of the logical regions; updating, by the controller, a translation data structure of the storage device, the translation data structure being updated to map any of the logical regions of the storage device to a respective physical portion of the storage device, the respective physical portion being selected based on the respective usage metric of the logical region, wherein the translation data structure is part of a flash translation layer of the storage device, and the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device.

Abstract: A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

Abstract: Systems and methods data storage device performance prediction based on garbage collection resources are described. The data storage device may process host storage operations and determine a valid fragment count parameter for a current or future data block. Based on the valid fragment count parameter a predicted performance value for host storage operations is determined and the host device is notified of the predicted performance value.

Abstract: Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.

Abstract: A storage device including a nonvolatile memory device is described. The storage device includes a controller that receives a write command and data from an external host device. The controller preferentially writes the data in an area based on a normal write policy when the data is associated with a normal write, and in an area based on a turbo write policy when the data is associated with a turbo write. The controller may also receive a read command, to read data from an area based on the read command, and output the data to the external host device. The controller may also move the data in response to move information of the read command when the read command is received together with move information.

Abstract: Techniques provide for managing data storage. The techniques involve in response to receiving a request for unmapping a logical storage unit associated with a first disk slice on a first physical disk and the first disk slice, determining information associated with the first disk slice; generating, based on the information, a first entry and a second entry corresponding to the first disk slice; adding the first entry into a queue of failed disk slices to enable data stored on the first disk slice to be cleared; and adding the second entry into a queue of free disk slices to enable the first disk slice to be mapped to a further logical storage unit. Accordingly, such techniques can remarkably improve the write I/O performance of the system and prolong the lifetime of the SSD.

Abstract: A method, a computing device, and a non-transitory machine-readable medium for allocating data compression activities in a storage system are provided. A method includes tracking, by a storage controller, computing resources corresponding to a storage server. The storage controller processes one or more host read requests to access data requested by one or more hosts, the processing of the one or more host read requests including decompressing the data requested by the one or more hosts from the storage server and providing the decompressed data to the one or more hosts. The storage controller determines an amount of available computing resources after processing the one or more host read requests. Based on the amount of available computing resources, the storage controller performs inline compression of a first portion of host write requests and background compression of a second portion of the host write requests.

Abstract: An interface is instantiated for receiving storage requests for storing data in a software-defined storage network using an append-only storage scheme. The interface receives requests that are agnostic of interfaces and hardware-specific details of the storage devices of the software-defined storage network. A request comprises an identifier of a data object to be stored in the software-defined storage network using the append-only storage scheme. Metadata is generated for the data object indicating that the data object is an append-only object; and the request is translated to instructions for storing the data object in the storage devices using the append-only storage scheme. The data object is stored at one of the plurality of storage devices based on the instructions. The metadata is updated to indicate a mapping between the data object and a stored location of the data object.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system performs an operation of recovering system data lost due to SPO when an SPO recovery operation is performed, and flushes recovered system data into the memory device after a first time point at which the operation of recovering the system data is completed and before a second time point at which a power off preparation request is received from a host.

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.