Abstract: A new snapshot of a storage volume is created by instructing computing nodes to suppress write requests. Storage nodes create a new snapshot for the storage volume by allocating a new segment to the new snapshot and finalizes and performs garbage collection with respect to segments allocated to the previous snapshot. Subsequent write requests to the storage volume are then performed on the segments allocated to the new snapshot. A segment maps segments to a particular snapshot and metadata stored in the segment indicates storage volume addresses of data written to the segment. The snapshots may be represented by a storage manager in a hierarchy that identifies an ordering of snapshots and branches to clone snapshots. Consistency points may be created by storage nodes transmitting sequence numbers assigned to write IOPs to the storage manager. Segments store the sequence numbers in metadata enabling rolling back to specific sequence numbers.

Abstract: A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.

Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.

Abstract: Embodiments include a controller, a memory system including the controller, and a method of operating the controller. The controller includes a buffer memory configured to store original data. The controller also includes a central processing unit configured to generate a first command for transmitting the original data to a memory device, generate a second command for receiving data from the memory device, and store the data in the buffer memory. The controller further includes a data comparator configured to compare the data stored in the buffer memory with the original data. The central processing unit is further configured to determine whether the memory device is defective according to a comparison result of the data comparator.

Abstract: A data storage system includes a memory including a plurality of memory cells; and control logic configured to receive a first data string and determine a data type of the first data string. If the first data string is a combination command, the control logic obtains a plurality of sub-commands based on the first data string. Meanwhile, the control logic receives a second data string, determines that it represents an address, and decodes the address. While decoding the address or otherwise processing the second data string, the control logic performs a system operation specified by one of the sub-commands. The control logic also performs a memory operation, specified by another of the sub-commands, on one or more of the plurality of memory cells in accordance with the decoded address.

Abstract: Systems, apparatuses, and methods related to media type selection for image data are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Image data inputs can be written (e.g., stored) in a particular type of memory media characteristics. For instance, selection of memory media can be based on one or more attributes of the image data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, image data from a first image sensor of a plurality of image sensors, identifying one or more attributes of the image data, and writing, based at least in part on the one or more attributes of the image data, the image data to a first memory media type of the plurality of memory media types.

Abstract: A system and method for prolonging lifespans of storage drives. The method includes determining an expected expiration time for each of a plurality of blocks, wherein each block includes data of a respective file, wherein the expected expiration of each block is determined based on a file type of the respective file; and writing a portion of data to at least one block of the plurality of blocks based on the expected expiration time for each block.

Abstract: A storage system with garbage collection prioritizes data segments for garbage collection in the storage memory. Priority of each data segment relates to amount of processing device work for garbage collection of the data segment versus benefit relating to amount of dead data to be reclaimed by garbage collection of the data segment. Garbage collection is performed according to the priority of each data segment.

Abstract: Embodiments described herein provide a method for accessing a host memory through non-volatile memory over fabric bridging with direct target access. A first memory access command encapsulated in a first network packet is received at a memory interface unit and from a remote direct memory access (RDMA) interface and via a network fabric. The first memory access command is compliant with a first non-volatile memory interface protocol and the first network packet is compliant with a second non-volatile memory interface protocol. The first network packet is unwrapped to obtain the first memory access command. The first memory access command is stored in a work queue using address bits of the work queue as a pre-set index of the first memory access command. The first memory access command is sent from the work queue based on the pre-set index to activate a first target storage device.

Abstract: Mapping information management for data storage devices is provided. A controller caches write data issued by a host in a temporary storage and then programs the cached write data from the temporary storage to a non-volatile memory. The controller uses a mapping information format to manage mapping information of logical addresses recognized by the host. As presented in the mapping information format, the values not greater than a first threshold value and mapped to the configuration information storage space of the non-volatile memory are at least partially used to point to the temporary storage, and the values greater than the first threshold value are mapped to the non-volatile memory.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include: a memory device including a memory cell array and a page buffer; and a memory controller including a write buffer. The memory device may further include a page buffer state determiner configured to generate a page buffer state signal based on a state of the page buffer and provide the page buffer state signal to the memory controller. The memory controller may further include a write operation controller configured to provide data provided from a host to either the page buffer or the write buffer in response to the page buffer state signal, and control the memory device to program data stored in the page buffer to the memory cell array based on the state of the write buffer.

Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on cell count information when correction of an error in read data, received from the memory device performing a read operation, fails. The memory controller may control the memory device to perform a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When correction of the error in the read data fails again, the memory controller may control the memory device to perform a read operation using a corrected read voltage generated using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.

Abstract: Techniques involve receiving a write request for writing metadata of a file system into a solid state disk having a multi-level cell, and then caching the to-be-written metadata into a memory. The techniques further involve sequentially writing the cached metadata into the solid state disk by redirect-on-write. Accordingly, there is a file system implemented for properties of a solid state disk having a multi-level cell. Such techniques are able to provide completely sequential write of metadata of the file system by supporting redirect-on-write, thereby reducing the write amplification of the solid state disk and improving the performance of the file system.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.

Abstract: An information handling system may include a processor and a read-only memory communicatively coupled to the processor and comprising a basic input/output system (BIOS)-accessible region of the read-only memory including a first subregion communicatively coupled to the processor via a first communications interface and a second subregion communicatively coupled to the processor via a second communications interface. The information handling system may also include the BIOS, configured to responsive to a read request from the processor to the BIOS-accessible region determine whether a memory address associated with the read request is within a decoding range of the first subregion, cause the processor to access the first subregion via the first communications interface if the memory address is within the decoding range, and cause the processor to access the second subregion via the second communications interface if the memory address is outside the decoding range.

Abstract: Exemplary methods, apparatuses, and systems include reading logical-to-physical (L2P) table entries from non-volatile memory into volatile memory. Upon detection of a trigger to recover L2P data that was unmerged with the L2P table entries, a copy of an L2P journal is read from non-volatile memory. The L2P journal includes the L2P data that was unmerged with the L2P table entries. One or more of the L2P table entries are updated using the L2P data from the L2P journal.

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Abstract: According to one embodiment, a storage system includes a first storage including first nonvolatile memories storing data which is corrupted when data is read from the first nonvolatile memories, and a controller which controls the first storage. The controller reads data from a first nonvolatile memory at a first address, and determines that whether the read data is to be written back to the first storage or not.

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.

Abstract: Methods, systems, and devices for performing an access operation on a memory cell, incrementing a value of a first counter based on performing the access operation on the memory cell, determining that the incremented value of the first counter satisfies a threshold, incrementing a value of a second counter based on determining that the incremented value of the first counter satisfies the threshold, and performing a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold are described.

Abstract: A storage system in one embodiment comprises a front-end device and a plurality of storage nodes. A given storage node of the plurality of storage nodes comprises at least one processor and memory. The front-end device is configured to obtain a write operation comprising at least a first data page and to generate a content-based signature based at least in part on the first data page. The front-end device is further configured to compress the first data page and to generate first compression information corresponding to the first data page. The first compression information comprises an indication that the first data page has been compressed. The front-end device is further configured to provide the generated content-based signature, the compressed first data page and the first compression information to the given storage node.

Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.

Abstract: Offloading device management responsibilities from a storage device in an array of storage devices, including: retrieving, from the storage device, control information describing the state of one or more memory blocks in the storage device; and performing, in dependence upon the control information, a storage device management operation.

Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes a read counter configured to store a block read count value of a super block and memory blocks within a non-super block as a status information in an internal memory by counting a number of times that a read operation is performed on the memory blocks; and a super block manager configured to: store a super block reclaim trigger reference and a non-super block reclaim trigger reference, which is set for the super block and the non-super block, as the status information in the internal memory, divide data stored in the memory blocks into hot data and cold data according to the block read count value, and copy the hot data in the non-super block to the super block according to the status information.

Abstract: A system including embedded storage devices is described. A method of system operation includes determining, by a processing device of a storage system controller operatively coupled via a network to embedded storage devices, that data is to be stored in a first storage portion of a first storage device of the embedded storage devices. The method also includes buffering the data in a second storage portion of a second embedded storage device of the embedded storage devices.

Abstract: Methods and apparatus related to enabling individual NVMe (Non-Volatile Memory express) IO (Input Output or I/O) queues on differing network addresses of an NVMe controller are described. In one embodiment, a plurality of backend controller logic is coupled to a plurality of non-volatile memory devices. One or more virtual controller target logic (coupled to the plurality of backend controller logic) transmit data from a first portion of a plurality of IO queues to a first backend controller logic of the plurality of the backend controller logic. The one or more virtual controller target logic transmit data from a second portion of the plurality of IO queues to a second backend controller logic of the plurality of backend controller logic. Other embodiments are also disclosed and claimed.

Abstract: A method of operating a memory comprises reading a first node including first data and a first link; writing the first data to a data collecting area; updating a first collecting link of the first data, which is written in the data collecting area to a position in the data collecting area; reading a second node corresponding to the first link, the second node including second data and a second link; and writing the second data to a position in the data collecting area, which is designated by the first collecting link.

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. The controller is configured to advertise a first logical memory capacity to a host device, wherein the first logical memory capacity is less than the physical memory capacity, determine that at least one of the memory regions is at or near end of life, and in response to the determination, (1) retire the at least one of the memory regions and (2) reduce a logical memory capacity of the host device to a second logical memory capacity that is less than the first logical memory capacity.

Abstract: According to one embodiment, when it is determined that a first storage device of a plurality of storage devices is to be removed and an additional storage device is connected to a storage controller, the storage controller writes update data portions corresponding to data portions already written to the first storage device to any storage device selected from remaining one or more storage devices of the plurality of storage devices except for the first storage device and the additional storage device. Further, the storage controller writes update data portions corresponding to data portions already written to the remaining one or more storage devices to any storage device selected from the remaining one or more storage devices and the additional storage device.

Abstract: A method of operating a memory is provided. The method includes, in response to an access of a block of memory updating a first queue to identify the accessed block in response to a determination that the block is not already identified in the first queue and a determination that the block is not already identified in a second queue, and updating the second queue to identify the accessed block of memory in response to a determination that the block is already identified in the first queue. The method further includes scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a threshold, and performing a read setup operation on a block of memory that has been identified as the read setup candidate.

Abstract: A semiconductor device comprises a data region including a plurality of first semiconductor chips and configured to store data requested by a host, and a metadata region including one or more second semiconductor chips and configured to store metadata corresponding to the plurality of first semiconductor chips in the data region. The data region and the metadata region are accessed using different signals to perform a command-based operation corresponding to a command signal.

Abstract: Various examples are directed to systems and methods for managing a memory device. Processing logic may identify a set of retired blocks at the memory device that were retired during use of the memory device. The processing logic may modify a first table entry referencing the first block to indicate that the first block is not retired. The processing logic may also modify a second table entry referencing the second block to indicate that the second block is not retired. The processing logic may also recreate a logical-to-physical table entry for a first page of at the first block, the logical-to-physical table entry associating a logical address with the first page.

Abstract: A memory system may comprise: a memory device including a plurality of memory dies; and a controller including a first memory, Wherein the controller may store data segments of user data, corresponding to a plurality of commands received from a host, in the first memory, controls the memory device to sequentially store the data segments in the memory dies through interleaving, may update map segments of map data corresponding to storage of the data segments in the memory dies, may store the map segments in the first memory, controls the memory device to store the map segments stored in the first memory in the memory dies, and may assist the host in storing the map segments, stored in the first memory, in a second memory in the host.

Abstract: The present disclosure relates to a storage device and a method of operating the same. The storage device includes a memory device including a memory cell array that stores normal data and map data, and a memory controller configured to control overall operation, including program operation, read operation, and erase operation, of the memory device in response to requests from a host. The memory device is configured to, during a map data load operation, transmit first map data to the memory controller by reading the first map data among the map data stored in the memory cell array, and transmit second map data to a page buffer group of the memory device by reading the second map data among the map data.

Abstract: One embodiment provides a system which facilitates operation of a storage system. During operation, the system receives, by a storage engine, a request to write data to a hard disk drive. The system determines metadata associated with the data. The system stores the metadata in a volatile memory associated with the storage engine. The system identifies a physical address in a first non-volatile solid-state memory to which to write the metadata, wherein the first non-volatile solid-state memory is accessible via a controller of the hard disk drive. The system writes the metadata to the first non-volatile solid-state memory based on the physical address. The system writes the data to the hard disk drive.

Abstract: An apparatus includes memory arrays and a power-performance-endurance manager module. The power-performance-endurance manager module stores a power-endurance state descriptor data structure, which includes endurance levels associated with power-endurance modes. The manager module dynamically configures the apparatus to operate the memory arrays according to one of the power-endurance modes based on a desired endurance level.

Abstract: A FPGA-based intelligent storage control system is provided that includes a FLASH main controller; a FLASH command former and an address generator with a memory function, for generating level signal of cross clock domain and automatically avoiding out-of-bounds writing. A configuration data former provides for driving and controlling a configuration writing in function by a writing configuration drive signal. An automatic reading configurator provides automatic configuration reading by internal drive signal to drive. A main data and auxiliary data former provides continuous storage of main data according to ping-pong operation for unequal width RAM operation. A FLASH data reading buffer and a multi-interface external drive module are also present. The system is applicable to an unmanned underwater vehicle and underwater acoustic equipment.

Abstract: A device is provided that includes a logic processor, a power storage cell, a sensor, a wireless logic and a power source. The power source is configured to harvest power in response to exposure to radio frequency (RF) energy using an antenna element of the device. The harvested power is transferred to the power storage cell such that when the power storage cell has a usable amount of power the logic processor (a) samples data using the sensor, (b) processes the sample data into a message that is encrypted, and (c) transmits the message using the wireless logic to an end node that is configured to receive the message from the device. When usable amount of power is not present in the power storage cell during any one of (a)-(c), data is saved in persistent memory until additional harvested power is present in the power storage cell.

Abstract: Example embodiments of the present invention relate and a method and an apparatus for double hashing. The method including receiving a hash signature, including a short hash handle, for a data block. The method then includes determining a bucket with which the hash signature should be associated and associating the hash signature with the bucket.

Abstract: An image forming apparatus includes a nonvolatile semiconductor storage device, a memory, and a processor. The processor is configured to exert control in such a manner that, when the nonvolatile semiconductor storage device is notified of deleted file data and a trim command is to be executed, even if an operation on file data stored in the nonvolatile semiconductor storage device is performed in the state in which the operation state of the image forming apparatus is set to the power-saving state, the trim command is not executed on the nonvolatile semiconductor storage device in accordance with the operation performed on file data.

Abstract: The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.

Abstract: A storage system and method for enabling a software-defined dynamic storage response are provided. In one embodiment, a controller of a storage system is configured to receive an expected response time from a host; in response to receiving the expected response time from the host, cache a logical-to-physical address table entry of a wordline; and store the cached logical-to-physical address table entry of the wordline as metadata in a next wordline along with host data. Other embodiments are provided.

Abstract: Systems and methods for operating a virtual memory area are provided. A dynamic address translation table for the virtual memory area is generated. A program is operated at a first computing machine until insufficient local real memory is available to complete operation. A request for real memory space is transmitted from the first computing machine to an additional computing machine. A location of a segment of the local real memory of the additional computing machine is received at the first computing machine and the dynamic address translation table is updated to associate a virtual address with the received location.

Abstract: The present disclosure generally relates to scheduling zone-append commands for a zoned namespace (ZNS). Rather than taking zone-append commands in order or randomly, the zone-append commands can be scheduled in the most efficient manner consistent with the open zones of the ZNS. A zone priority is determined based upon the length of time that a zone has been open together with the zone status. Generally, the older the zone and/or the more full that a zone is increases the priority. Once the zone priority is established, the zone-append commands are scheduled to ensure the zone-append commands for the high priority zones are processed first so that the open zone can be filled prior to closing.

Abstract: A group of sectors of a memory is provisioned for a logical volume such that an unprovisioned capacity of the memory interleaves at least a subset of the group of sectors to provide proximity disturb isolation. A request to access the memory is received, the request including a logical address within the logical volume. A sector within the group of sectors is identified, the sector corresponding to the logical address, and the requested access is performed in the sector within the group of sectors.

Abstract: The present invention provides a circuitry including a processor, a one-time programmable memory and an access control circuit. The one-time programmable memory includes a first area and a first access control data, wherein the first access control data is used to indicate whether the first area can be written or read by the processor. When the processor writes or reads the first area through the access control circuit, the access control circuit determines whether to write or read the first area according to the first access control data, and the access control circuit determines what kind of data for sending back to the processor.

Abstract: In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host.

Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.