Programmable Read Only Memory (prom, Eeprom, Etc.) Patents (Class 711/103)
  • Data erase operations for a memory system
    Patent number: 11443811
    Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Brandt, Adam J. Hieb, Jonathan Tanguy, Preston A. Thomson
  • Apparatus and method for engaging a plurality of memory systems with each other
    Patent number: 11442628
    Abstract: A data processing system includes a host configured to handle data in response to an input received by the host, and a plurality of memory systems engaged with the host and configured to store or output the data in response to a request generated by the host. A first memory system among the plurality of memory systems can perform generation, erasure, or updating of metadata for the plurality of memory systems.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Ik-Sung Oh
  • Storage device sharing attribute information with host device to use host memory buffer and electronic device including the same
    Patent number: 11435943
    Abstract: A storage device includes a memory device and a controller. The memory device stores attribute information associated with a host memory buffer allocated on a host memory. The controller communicates with the host memory such that a plurality of pieces of data associated with operations of the memory device is buffered, based on the attribute information, in a plurality of host memory buffers allocated on the host memory. The controller communicates with the host memory such that first data corresponding to a first attribute group managed in the attribute information is buffered in a first host memory buffer among the plurality of host memory buffers and second data corresponding to a second attribute group different from the first attribute group is buffered in a second host memory buffer separate from the first host memory buffer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: September 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jison Im, Hyunseok Kim, Hyun-Sik Yun, Hoju Jung
  • Rebuild directory/block allocation map from embedded data block information in file system disk
    Patent number: 11436101
    Abstract: According to one general aspect, an apparatus may include a storage element configured to store both data and metadata, wherein each piece of data is associated with and stored with a corresponding piece of metadata. The apparatus may include a controller processor. The controller processor may be configured to, in response to a piece of data being written to the apparatus: generate a piece of metadata that includes a set of parameters to facilitate a at least partial repair of a block information map, and embed the piece of metadata with the corresponding piece of data.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 6, 2022
    Inventors: Jian Zhao, Hui-Juan Li, Rong Zheng
  • Mechanism for updating host file system and flash translation layer based on underlying NAND technology
    Patent number: 11436023
    Abstract: A method of operating a storage system is provided. The method includes executing an operating system on one or more processors of a compute device that is coupled to one or more solid-state drives and executing a file system on the one or more processors of the compute device. The method includes configuring the compute device with one or more replaceable plug-ins that are specific to the one or more solid-state drives, and executing a flash translation layer on the one or more processors of the compute device, with assistance through the one or more replaceable plug-ins for reading and writing the one or more solid-state drives.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 6, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Russell Sears, Hari Kannan, Yuhong Mao
  • Storage controller and storage device including the same and operating method thereof
    Patent number: 11435903
    Abstract: The present disclosure provides an operating method of a storage controller. The operating method includes receiving user data and environmental information, obtaining logical-characteristic information and physical-characteristic information, defining a current state, obtaining expectation values, and performing a write operation. User data and environmental information is received from a non-volatile memory. The current state may be defined based on the logical-characteristic information and the physical-characteristic information. Expectation values may be obtained based on policy information and the current state. The write operation may be performed on the user data through a physical stream corresponding to a maximum value among the expectation values.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungjun Yang, Kibeen Jung, Byeonghui Kim, Jungmin Seo
  • Memory controller and method of operating the same
    Patent number: 11436148
    Abstract: A memory controller may include a host interface controller, a first queue, a second queue, and a cache memory. The host interface controller may be configured to generate, based on a request received from a host, one or more command segments corresponding to the request. The first queue may be configured to store the one or more command segments. The second queue may be configured to store a target command segment from among the one or more command segments. The memory controller caches a target map segment corresponding to the target command segment into the cache memory in response to the target command segment being transferred from the first queue to the second queue.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Gi Jo Jeong
  • Memory control system for setting garbage collection frequency higher in dirty mode
    Patent number: 11436140
    Abstract: A memory system may include a memory device including a plurality of memory blocks and a controller suitable for determining whether to change from a normal mode to a dirty mode based on a size of free space of a host a sum of an amount of restoration of garbage collection for victim blocks and a size of all free blocks in the memory device. In the dirty mode, the controller controls the memory device to perform a garbage collection operation on the victim blocks at a frequency greater than frequency at which a garbage collection operation is performed in the normal mode.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyeong Ju Na
  • System, method and computer program product for instantiating blocks of a solid-state disk to include different flash characteristics
    Patent number: 11435902
    Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kaoutar El Maghraoui, Hubertus Franke, Hillery C. Hunter, Gokul Bhargava Kandiraju, Hartmut Erhard Penner
  • Memory system including non-volatile buffer and control method thereof
    Patent number: 11436136
    Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: September 6, 2022
    Assignee: Kioxia Corporation
    Inventors: Takehiko Amaki, Toshikatsu Hida, Shunichi Igahara, Yoshihisa Kojima, Suguru Nishikawa
  • Memory cells configured to generate weighted inputs for neural networks
    Patent number: 11437103
    Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Minucci, Tommaso Vali, Fernanda Irrera, Luca De Santis
  • Pre-operating system environment-based sanitization of storage devices
    Patent number: 11436367
    Abstract: A technique includes, in a pre-operating system environment of a computer system, a hardware processor of the computer system executing machine executable instructions to determine whether a sanitization option was selected in a prior operating system environment of the computer system. In response to determining that the sanitization option was selected, the hardware processor executes the instructions in the pre-operating system environment to determine, for an adapter of the computer system, a storage inventory associated with the adapter and sanitize the storage inventory.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 6, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sriram Subramanian, Scotty M. Wiginton
  • Memory apparatus and control method for command queue based allocation and management of FIFO memories
    Patent number: 11435945
    Abstract: According to one embodiment, a memory apparatus includes a memory device and a controller. The memory device includes a plurality of memory chips. The controller includes a plurality of memories. The controller determines whether or not the memory chip is allocated to any one memory when receiving an access request related to the memory chip from a host apparatus. The controller newly allocates the memory chip to the memory to which none of the memory chips is allocated when it is determined that the memory chips is not allocated, and enqueues a command corresponding to the access request received from the host apparatus to the memory to which the memory chip is newly allocated.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hajime Yamazaki, Mitsunori Tadokoro
  • Geometry-aware command scheduling
    Patent number: 11435908
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
  • Semiconductor memory device, memory system, and write method
    Patent number: 11437095
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: September 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Yasuyuki Matsuda
  • Information processing apparatus
    Patent number: 11429306
    Abstract: A comparison unit configured to compare volume of unnecessary data of a first semiconductor memory to a threshold of the first semiconductor memory, which is set in advance, and a transmission unit configured to transmit a delete command to the first semiconductor memory in accordance with a comparison result indicating that the volume of the unnecessary data of the first semiconductor memory is larger than the threshold of the first semiconductor memory are provided, and the transmission unit transmits a delete command to the second semiconductor memory upon transmission of the delete command to the first semiconductor memory.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 30, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takehiro Ito
  • Replicating and managing aggregated descriptive data for cloud services
    Patent number: 11429453
    Abstract: Disclosed are various embodiments for replicating and maintaining aggregated descriptive data for cloud services. In one embodiment, updates to descriptive data that describes a resource of a customer provided by a cloud service are received by an aggregated descriptive data service from a backend service. An aggregated descriptive data store is then updated by the aggregated descriptive data service based at least in part on the received updates.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 30, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Richard Hamman, Kevin Pakiry, Gareth Lennox, Fernand Sieber, Thomas George Mathew, Pavel Tcholakov, Graeme Kruger, Bhavani Morarjee, Tarek Khaled Ismail Eltalawy, Sara Mohamed Ali, Paul Maree
  • Method and system of reducing address mapping space of flash translation layer
    Patent number: 11429533
    Abstract: A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 30, 2022
    Assignee: SHENZHEN UNIONMEMORY INFORMATION SYSTEM LIMITED
    Inventors: Jian Zuo, Yuanyuan Feng, Zhiyuan Leng, Jintao Gan, Weiliang Wang, Zongming Jia
  • Read level edge find operations in a memory sub-system
    Patent number: 11429483
    Abstract: A processing device performs operations including receiving a request to locate one or more distribution edges of one or more programming distributions of a memory cell, the request specifying a target error rate for the one or more programming distributions, measuring at least one error rate sample of a first programming distribution selected from the one or more programming distributions, and determining a location of a first distribution edge of the first programming distribution at the target error rate based on a comparison of the at least one error rate sample of the first programming distribution against the target error rate.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Larry J. Koudele
  • Memory control method, memory storage device, and memory control circuit unit
    Patent number: 11430538
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 30, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Pochiao Chou, Cheng-Che Yang
  • Split cache for address mapping data
    Patent number: 11429528
    Abstract: Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicola Colella, Antonino Pollio
  • System and method for facilitating reduction of latency and mitigation of write amplification in a multi-tenancy storage drive
    Patent number: 11429519
    Abstract: During operation, the system receives a chunk of data to be written to a non-volatile memory, wherein the chunk includes a plurality of sectors. The system assigns consecutive logical block addresses (LBAs) to the plurality of sectors. In response to determining that a first sector is associated with an existing stream for the chunk, the system appends the first sector to one or more other sectors stored in a first buffer associated with the existing stream. The system detects that a total size of the stored sectors in the first buffer is the same as a first size of a physical page in the non-volatile memory. The system writes the stored sectors from the first buffer to the non-volatile memory at a first physical page address. The system creates, in a data structure, a first entry which maps the LBAs of the written sectors to the first physical page address.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 30, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Method of demand scrubbing by placing corrected data in memory-side cache
    Patent number: 11429480
    Abstract: Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bryan Hornung, David Patrick
  • Automatic data separation and placement for compressed data in a storage device
    Patent number: 11429279
    Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs; the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 30, 2022
    Inventors: Jingpei Yang, Jing Yang, Rekha Pitchumani
  • Efficient copying of data in a storage system
    Patent number: 11422714
    Abstract: Optimizing copy operations in a storage array, including: receiving a plurality of copy operations; detecting a triggering event that causes a storage array controller to initiate execution of the plurality of copy operations; and combining, in dependence upon a metadata optimization policy, the plurality of copy operations into a single copy operation.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: August 23, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Christopher Golden, Scott Smith, Luke Paulsen, David Grunwald, Jianting Cao
  • Memory system having memory device and controller
    Patent number: 11422746
    Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 23, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Takehiko Amaki
  • Multi-storage device lifecycle management system
    Patent number: 11422723
    Abstract: A multi-storage device lifecycle management system includes a server computing system having a plurality of devices and an operating system engine. The operating system engine identifies an estimated first device remaining lifetime for a first device, identifies an estimated second device remaining lifetime for a second device, and determines whether a difference between the estimated first device remaining lifetime and the estimated second device remaining lifetime is less than an estimated multi-device minimum end-of-lifetime difference. If so, the computing system distributes workload operations between the first device and the second device in order to cause the difference between the estimated first device remaining lifetime and the estimated second device remaining lifetime to be greater than or equal to the estimated multi-device minimum end-of-lifetime difference.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 23, 2022
    Assignee: Dell Products L.P.
    Inventors: Wei Dong, Haifang Zhai
  • Information processing device, information processing method, and recording medium
    Patent number: 11422538
    Abstract: An information processing device according to the present invention includes: a memory; and at least one processor coupled to the memory. The processor performing operations. The operations includes: constructing second data that is acquired, based on first data containing a plurality of observation values in a plurality of times, by stacking the first data with respect to the times, and extracting a constant pattern that is a combination of the observation values having temporal constancy in the first data, based on the second data; generating a difference between the first data and the constant pattern in the time; and extracting a random pattern that is a combination of the observation values without temporal constancy, based on the difference.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 23, 2022
    Assignee: NEC CORPORATION
    Inventor: Tsubasa Takahashi
  • Addressing zone namespace and non-zoned memory based on data characteristics
    Patent number: 11422745
    Abstract: A memory device comprises a first region configured as non-zoned addressable memory and a second region configured as a zone namespace. A write command comprising a payload and a functional designation of the payload is received, wherein the functional description indicates whether the payload comprises sequentially-writable data. Based on the functional designation of the payload, a corresponding one of the first region or the second region of the memory device is determined, wherein the second region is to store sequentially-writable data. The payload is stored in the corresponding one of the first region or the second region of the memory device.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Spare substitution in memory system
    Patent number: 11422884
    Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Thomas Pawlowski
  • Memory array reset read operation
    Patent number: 11423976
    Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
  • Garbage collection method and storage device
    Patent number: 11416162
    Abstract: The present application relates to a garbage collection method and a storage device for reducing write amplification. A method for selecting a data block to be collected in garbage collection, including: obtaining, according to a first selection policy, a first data block to be collected; determining, according to a first rejection policy, whether to refuse to collect the first data block to be collected; and if according to the first rejection policy, rejection to collect of the first data block to be collected is determined, not performing garbage collection on the first data block to be collected.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 16, 2022
    Assignee: BEIJING MEMBLAZE TECHNOLOGY CO., LTD
    Inventors: Jinyi Wang, Xiangfeng Lu
  • Method and apparatus for cache slot allocation based on data origination location or final data destination location
    Patent number: 11416407
    Abstract: Operational information in a storage system is collected regarding storage media storage tiers, devices, drives, tracks on drives, and logical storage layers, to determine an estimated amount of time it will take to write data from cache to the intended drive when a new write operation arrives at the storage system. This information is then used to decide which type of cache is most optimal to store the data for the write operation, based on the estimated amount of time it will take to write data out from the cache. By allocating cache slots from a faster cache to write operations that are expected to quickly be written out to memory, and allocating cache slots from the slower cache to write operations that are expected to take more time to be written out to memory, it is possible to increase the availability of the cache slots in the faster cache.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 16, 2022
    Assignee: Dell Products, L.P.
    Inventor: John Creed
  • Method and resource scheduler for enabling a computing unit to map remote memory resources based on optical wavelength
    Patent number: 11416299
    Abstract: A method and a resource scheduler for enabling a computing unit to use memory resources in a remote memory pool. The resource scheduler allocates a memory unit in the remote memory pool to the computing unit for usage of memory resources in the allocated memory unit, and assigns an optical wavelength for communication between the computing unit and the allocated memory unit over an optical network. The resource scheduler further configures at least the computing unit with a first mapping between the assigned optical wavelength and the allocated memory unit. Thereby, the optical network can be utilized efficiently to achieve rapid and reliable communication of messages from the computing unit to the allocated memory unit.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 16, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Joao Monteiro Soares, Chakri Padala, Amir Roozbeh, Mozhgan Mahloo
  • Memory sub-system logical block address remapping
    Patent number: 11416388
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Vamsi Pavan Rayaprolu, Karl D. Schuh, Jiangang Wu, Gil Golov
  • Enablement of software defined storage solution for NVME over ethernet fabric management on storage controller
    Patent number: 11416428
    Abstract: A computer system includes a BMC and a host of the BMC. The BMC receives a first message from a first remote device on a management network. The BMC determines whether the first message is directed to a storage service or fabric service executed on a main processor of a storage controller of the host. The host is a storage device. The storage controller includes an RDMA controller in communication with the main processor through an internal communication channel of the storage controller. The RDMA controller is managed by the storage service. The BMC extracts a service management command from the first message, when the first message is directed to the storage service or fabric service. The BMC sends, through a BMC communication channel established for communicating baseboard management commands between the BMC and the host, a second message containing the service management command to the host.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 16, 2022
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Anurag Bhatia, Jason Messer, Sanjoy Maity
  • Zone formation for zoned namespaces
    Patent number: 11416161
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The media unit comprises a plurality of dies, and each of the plurality of dies comprising a plurality of erase blocks. The controller is configured to compare an estimated age of a first available erase block in each of the plurality of dies to one another and select one or more of the first available erase blocks from one or more dies of the plurality of dies based on the estimated ages to form a first zone. At least one first available erase block from at least one die of the plurality of die is excluded from the first zone.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alan D. Bennett, Liam Parker, Daniel L. Helmick, Sergey Anatolievich Gorobets, Peter Grayson
  • Memory sub-system storage mode control
    Patent number: 11416177
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The memory device can include memory cells. The processing device can store operation system data in the memory cells in a single level cell (SLC) mode. The processing device can assert a flag indicating that the data written to the memory cells in the SLC mode is to remain stored in the SLC mode. The processing device can de-assert the flag, thereby indicating that the data is foldable into memory cells in a non-SLC mode.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Thomas Pratt
  • Phase change memory system, phase change memory device, and phase change memory device refresh method
    Patent number: 11417395
    Abstract: A phase change memory system comprises a phase change memory device which includes a plurality of memory units including a plurality of memory cells in units of at least one or more codewords and a phase change memory controller which performs a chip refresh operation for refreshing the entire phase change memory device, wherein the phase change memory device includes a setting circuitry which determines one of the plurality of memory units in a desired manner, a refresh controller which refreshes the decided memory unit, a sensing circuitry which senses data of at least one or more codewords included in the refreshed memory unit, and a request circuitry which requests a host for the chip refresh operation on the basis of a result of the sensing operation.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon Sung Shin, Kwang Jin Lee
  • Managing garbage collection in a memory subsystem based on characteristics of data streams
    Patent number: 11416389
    Abstract: A method for managing garbage collection in a memory subsystem, where a stream data manager writes data units from a stream of data into an allocated portion of memory composed of a plurality of blocks. The stream data manager evaluates a behavior of the stream of data to calculate the stream's efficiency, where the efficiency value is calculated based on an amount of invalid data units stored in the allocated portion of memory. The stream data manager determines a threshold of valid data units in a block within the allocated portion of memory, applicable to each block in the plurality of blocks for determining when to perform garbage collection. The stream data manager performs the garbage collection of a first block of the plurality of blocks in response to determining that a value of valid data units in the first block is within a predetermined range of the threshold value.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 16, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: William Akin, Shirish D. Bahirat
  • Electronic device
    Patent number: 11416691
    Abstract: An electronic device includes a card interface and a processing module. The card interface is electrically connected to the processing module, and a SIM card or a memory card may be inserted into the card interface. The card interface includes 8 springs, where N>1; when a memory card is inserted into the card interface, the memory card is electrically connected to the processing module; and when a SIM card is inserted into the card interface, the SIM card is electrically connected to the processing module, and one metal pin of the SIM card is electrically connected to a first spring in the N springs and one spring adjacent to the first spring. The processing module is configured to determine, based on at least a level of the first spring, that an inserted card is a SIM card or a memory card.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 16, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Jiangtao Yang
  • Partially written block treatment
    Patent number: 11416154
    Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
  • Estimating worker nodes needed for performing garbage collection operations
    Patent number: 11409652
    Abstract: Systems and methods for estimating the number of workers needed to perform a garbage collection operation are disclosed. Similarity groups are used to identify segments associated with objects in a computing system. Using deletion records that identify objects to be deleted, the similarity groups impacted by the deletion records can be identified. The number of workers can be determined based on the impacted similarity groups. More specifically, the number of impacted similarity groups and/or workers can be evaluated in terms of memory requirements, input/output constraints and/or time requirements to estimate the number or workers needed to clean similarity groups impacted by a garbage collection operation.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 9, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Nicholas A Noto, Mariah Arevalo, Philip Shilane, Joseph S. Brandt
  • Semiconductor memory device and manufacturing method of the semiconductor memory device
    Patent number: 11411022
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell stack structure surrounding a first channel structure and a second channel structure; a first source select line overlapping with a first region of the cell stack structure and surrounding the first channel structure; and a second source select line overlapping with a second region of the cell stack structure and surrounding the second channel structure. Each of the first source select line and the second source select line includes a first select gate layer overlapping with the cell stack structure, a second select gate layer disposed between the first select gate layer and the cell stack structure, and a third select gate layer disposed between the first select gate layer and the second select gate layer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Memory system and method of controlling nonvolatile memory and for reducing a buffer size
    Patent number: 11409467
    Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: August 9, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Memory system
    Patent number: 11409442
    Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
  • Storage system and method for using proactive device timeout information
    Patent number: 11409468
    Abstract: A storage system and method for using proactive device timeout information are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a command from a host; determine whether the command can be executed within a time-out window; and in response to determining that the command cannot be executed within the time-out window, send a request to the host to extend the time-out window. Other embodiments are provided.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: August 9, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Access control in CMB/PMR virtualization environment
    Patent number: 11409466
    Abstract: In one embodiment, a method provides access to a data storage device from a host coupled to the data storage device. The host is running a plurality of virtual functions. The method includes receiving an inbound request to a memory of a storage device controller of the data storage device. The memory of the storage device controller includes a DRAM memory and a non-DRAM memory. Whether the inbound request is a CMB/PMR transaction request is determined. The CMB/PMR transaction request is scheduled. Whether the scheduled CMB/PMR transaction request is allowed is determined. The allowed CMB/PMR transaction request is issued toward the DRAM memory of the storage device controller.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: August 9, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Increasing sizes of buckets of a fingerprint index
    Patent number: 11403020
    Abstract: In some examples, a system performs data deduplication using a fingerprint index comprising a plurality of buckets, each bucket of the plurality of buckets comprising entries associating fingerprints for data units to storage location indicators of the data units, wherein a storage location indicator of the storage location indicators provides an indication of a storage location of a data unit in persistent storage. For adding a new fingerprint to the fingerprint index, the system detects that a corresponding bucket of the plurality of buckets is full, in response to the detecting, adds space to the corresponding bucket by taking a respective amount of space from a further bucket of the plurality of buckets, and inserts the new fingerprint into the corresponding bucket after increasing the size of the corresponding bucket.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 2, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sudhanshu Goswami, Sonam Mandal
  • Host-controlled garbage collection
    Patent number: RE49162
    Abstract: In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 9, 2022
    Assignee: Kioxia Corporation
    Inventor: Sie Pook Law