Dynamic Random Access Memory Patents (Class 711/105)
Refresh scheduling (Class 711/106)
  • Code generator and decoder for communications systems operating using hybrid codes to allow for multiple efficient uses of the communications systems
    Patent number: 9264069
    Abstract: A method of encoding data for transmissions from a source to a destination over a communications channel is provided. The method operates on an ordered set of source symbols and may generate zero or more redundant symbols from the source symbols, wherein data is encoded in a first step according to a simple FEC code and in a second step, data is encoded according to a second FEC code, more complex than the first FEC code. The first FEC code and/or the second FEC code might comprise coding known in the art. These steps result in two groups of encoded data in such a way that a low-complexity receiver may make use of one of the groups of encoded data while higher complexity receivers may make use of both groups of encoded data.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: February 16, 2016
    Assignee: Digital Fountain, Inc.
    Inventors: Mark Watson, Michael G. Luby
  • Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times
    Patent number: 9261940
    Abstract: A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-geun Kim, Kye-hyun Kyung, Jae-yong Jeong, Seung-hun Choi, Seok-cheon Kwon, Chul-ho Lee
  • Method for information processing and electronic apparatus thereof
    Patent number: 9258774
    Abstract: A method for information processing and an electronic device thereof are provided. The method includes: obtaining, in the case that a first application runs, a first control operation for the first application; during a process for establishing a group in response to the first control operation, controlling a first wireless communication module to serve as a wireless access point and naming the wireless access point with parameter information for the first group; establishing, after response information is obtained, a communication path directly connected to at least one second electronic device, the response information being response information generated in the case that the at least one second electronic device scans and selects the wireless access point; and obtaining, via the communication path, information indicating that the at least one second electronic device joins the first group.
    Type: Grant
    Filed: March 30, 2014
    Date of Patent: February 9, 2016
    Assignees: Beijing Lenovo Software Ltd., Lenovo (Beijing) Co., Ltd.
    Inventors: Hui Wang, Shaowei Chen, Lei Zhao, Yu Chen, Min Yin, Dongping Huang, Pengfei Hao
  • Prioritizing read-command issuance in a data storage apparatus
    Patent number: 9235504
    Abstract: According to one embodiment, a storage control apparatus includes an interface and a controller. The interface transfers data or a command to or from a nonvolatile memory including a storage area for each of banks. The controller controls read operations for the banks in accordance with generation of access requests to the banks, respectively. The controller prioritizes performing read-command issuance processing included in each of the read operations.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun Ichishima, Norifumi Tsuboi
  • Detection method and apparatus for hot-swapping of SD card
    Patent number: 9223739
    Abstract: A detection method for hot-swapping of a Secure Digital (SD) card is provided. The detection method includes steps of: transmitting an inquiry command to an card reader at a predetermined frequency; receiving a command return message replied in response to the inquiry command; determining whether the SD card is removed or plugged according to the command return message; and detecting a hot-swapping status of the SD card in real-time to provide an accurate status of the SD card for upper-layer applications.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: December 29, 2015
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventor: De-Jun Yu
  • Storage device command interval controller
    Patent number: 9218284
    Abstract: In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: December 22, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Tony Yoon, Akio Goto, Chi Kong Lee, Masayuki Urabe
  • Method and apparatus for delay compensation in data transmission
    Patent number: 9209961
    Abstract: A method and apparatus for delay compensation in data transmission is disclosed. In one embodiment, an IC is configured to transmit data along with a clock signal to which the data is synchronized at the receiver. The IC includes a delay circuit configured to receive the data, which is transmitted in beats. The delay circuit includes a number of pipelines corresponding to the number of beats. Beats of data input into the delay circuit are routed to particular ones of the pipelines in accordance with a desired amount of delay. The delay applied to the data may be set to align the data with the clock signal at the receiver and to compensate for inherent delays that affect the clock signal.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 8, 2015
    Assignee: Apple Inc.
    Inventor: Rakesh L. Notani
  • Semiconductor integrated circuit
    Patent number: 9183899
    Abstract: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: November 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae II Kim
  • Configurable memory circuit system and method
    Patent number: 9171585
    Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 27, 2015
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastien Smith, David T. Wang, Frederick Daniel Weber
  • Memory management unit for managing a state of memory, image processing device, and integrated circuit
    Patent number: 9165636
    Abstract: A memory management unit manages a state of a memory which is to be accessed by bank interleaving. The memory includes p banks (where p is an integer of 2 or greater). The memory management unit includes a control unit that dynamically determines a bank to be accessed from among the p banks. When predetermined conditions for a reserving state of the memory are satisfied and there is any unused bank in the p banks, the control unit performs power consumption reduction to control the memory to cause power consumption of the unused bank(s) to be less than power consumption of other banks in the p banks except the unused bank(s).
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: October 20, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Muroyama, Miho Tokieda, Shinichi Takada, Koji Yamada
  • Self terminated dynamic random access memory
    Patent number: 9158726
    Abstract: A method for operating a memory system and a memory buffer device. The method includes receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, and receiving an ODT signal from the CPU to a command port of the buffer device. Buffer device provides the self-termination information internally to the common data bus by automatically detecting the read or write command on the common command bus and adjust the termination resistor array in a pre-determined value and timing fashion so that information can be read from or write to a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface. All DIMM devices other than the DIMM device being read can be maintained in a termination state to prevent any signal from traversing to the common the common data bus interface.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: October 13, 2015
    Assignee: Inphi Corporation
    Inventor: Chao Xu
  • Data flows and their interaction with control flows
    Patent number: 9158580
    Abstract: A method and apparatus for processing data by a computer and a method of determining data storage requirements of a computer for earning out a data processing task.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 13, 2015
    Assignee: Cognovo Limited
    Inventor: Erkut Uygun
  • Semiconductor memory device which stores plural data in a cell
    Patent number: 9142299
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Sharing a check bit memory device between groups of memory devices
    Patent number: 9141472
    Abstract: A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 22, 2015
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, Ian Shaeffer
  • Dynamically partition a volatile memory for a cache and a memory partition
    Patent number: 9128845
    Abstract: A hybrid memory has a volatile memory and a non-volatile memory. The volatile memory is dynamically configurable to have a first portion that is part of a memory partition, and a second portion that provides a cache for the non-volatile memory.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 8, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jichuan Chang, Parthasarathy Ranganathan
  • Dynamic memory performance throttling
    Patent number: 9104540
    Abstract: Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misalignment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Brian Toronyi, Kenneth Shoemaker
  • Multi-input memory command prioritization
    Patent number: 9098203
    Abstract: Embodiments of the present disclosure provide a method and system for prioritizing memory commands. A priority determination engine determines a priority of a memory access command based on a plurality of inputs related to characteristics of the memory access command and a plurality of inputs related to a state of the memory. An access scheduler selects an order in which to issues the memory commands based at least on the priority. The priority determination is determined such that bandwidth utilization is improved.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 4, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Ron Kedem
  • DMA vector buffer
    Patent number: 9092429
    Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 28, 2015
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Andrew J. Higham, Michael S. Allen, John L. Redford
  • Two-level system main memory
    Patent number: 9087584
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 21, 2015
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
  • Multi-level memory controller with probability-distribution-based encoding
    Patent number: 9053051
    Abstract: A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: June 9, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Aditya Ramamoorthy, Zining Wu, Pantas Sutardja
  • WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES
    Publication number: 20150149716
    Abstract: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.
    Type: Application
    Filed: June 18, 2014
    Publication date: May 28, 2015
    Inventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
  • NONVOLATILE RANDOM ACCESS MEMORY USE
    Publication number: 20150149715
    Abstract: For nonvolatile random access memory (NVRAM) use, a query module identifies persistent data on a NVRAM in response to waking the NVRAM. A management module makes available the persistent data for use.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: LENOVO (Singapore) PTE, LTD.
    Inventor: Mark Charles Davis
  • CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET
    Publication number: 20150149714
    Abstract: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventors: Seth H. Pugsley, Robert L. Scott, Zeshan A. Chishti, Peng-Fei Chuang, Khun Ban, Christopher B. Wilkerson, Shih-Lien L. Lu, Kingsum Chow
  • Tagging in memory control unit (MCU)
    Patent number: 9037811
    Abstract: Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Glenn D. Gilda, Mark R. Hodges, Vesselina K. Papazova, Eric E. Retter
  • SEMICONDUTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20150134895
    Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.
    Type: Application
    Filed: August 22, 2014
    Publication date: May 14, 2015
    Inventors: Young-Soo SOHN, Chul-Woo PARK, Kwang-Il PARK, Hak-Soo YU
  • MECHANISMS TO ACCELERATE TRANSACTIONS USING BUFFERED STORES
    Publication number: 20150134896
    Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 14, 2015
    Inventors: ALI-REZA ADL-TABATABAI, YANG NI, BRATIN SAHA, VADIM BASSIN, GAD SHEAFFER, DAVID CALLAHAN, JAN GRAY
  • Memory arbitration system and method having an arbitration packet protocol
    Patent number: 9032166
    Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Jeddeloh, Ralph James
  • Online classification of memory pages based on activity level represented by one or more bits
    Patent number: 9032398
    Abstract: Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The method includes the steps of scanning page table entries of hypervisor-managed page tables continuously over repeating scan periods to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page. The activity level of the memory page may be represented by one or more bits of its page table entry and may be classified as having at least two states ranging from hot to cold.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: May 12, 2015
    Assignee: VMware, Inc.
    Inventors: Irfan Ahmad, Carl A. Waldspurger, Alexander Thomas Garthwaite, Kiran Tati, Pin Lu
  • Memory controller for memory with mixed cell array and method of controlling the memory
    Patent number: 9032136
    Abstract: A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bing Dai, Chung H. Lam, Jing Li
  • Methods of operating a memory system that include outputting a data pattern from a sector allocation table to a host if a logical sector is indicated as being erased
    Patent number: 9032134
    Abstract: A method of operating a memory system includes receiving a read command from a host, where the read command is associated with a logical sector of a memory, determining whether the logical sector of the memory is indicated as being erased in a sector allocation table, if the logical sector of the memory is indicated as being erased, outputting a data pattern from the sector allocation table to the host, and if the logical sector of the memory is not indicated as being erased, reading a physical sector of the memory and outputting data from the physical sector of the memory to the host.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sergey Anatolievich Gorobets
  • Memory expansion using rank aggregation
    Patent number: 9026714
    Abstract: In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping at a rank aggregator, the logical rank to one of a plurality of physical ranks at the memory modules, and forwarding the request to one of the memory modules according to the mapping. Two or more of the memory modules are combined to represent the number of logical ranks at the memory controller such that there is a one-to-one mapping between the logical ranks and the physical ranks. An apparatus for rank aggregation is also disclosed.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: May 5, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Jay Evan Scott Peterson, Philip Manela
  • Memory buffers and modules supporting dynamic point-to-point connections
    Patent number: 9025409
    Abstract: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: May 5, 2015
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Signal control device and signal control method
    Patent number: 9026746
    Abstract: A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively; an address collision detection unit detecting collision between addresses in which the first and second CPUs respectively read and write the data signal from and to the dual port RAM; a first storage unit storing the data signal read by the first CPU; a second storage unit storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM when the collision between the addresses is detected; and a switching unit switching a reading source outputting the data signal to the port to which the first CPU is connected and outputting the read data signal to the first CPU entering a readable state.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 5, 2015
    Assignee: Sony Corporation
    Inventor: Shinjiro Tanaka
  • Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals
    Patent number: 9026725
    Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Alexey Kostinsky, Zvika Greenfield, Christopher P. Mozak, Pavel Konev, Olga Fomenko
  • Data read/write system
    Patent number: 9026726
    Abstract: The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: May 5, 2015
    Assignee: Montage Technology (Shanghai) Co., Ltd.
    Inventors: Haiyang Li, Qingjiang Ma
  • TRACING MECHANISM FOR RECORDING SHARED MEMORY INTERLEAVINGS ON MULTI-CORE PROCESSORS
    Publication number: 20150120996
    Abstract: A memory race recorder (MRR) is provided. The MRR includes a multi-core processor having a relaxed memory consistency model, an extension to the multi-core processor, the extension to store chunks, the chunk having a chunk size (CS) and an instruction count (IC), and a plurality of cores to execute instructions. The plurality of cores executes load/store instructions to/from a store buffer (STB) and a simulated memory to store the value when the value is not in the STB. The oldest value in the STB is transferred to the simulated memory when the IC is equal to zero and the CS is greater than zero. The MRR logs a trace entry comprising the CS, the IC, and a global timestamp, the global timestamp proving a total order across all logged chunks.
    Type: Application
    Filed: March 30, 2012
    Publication date: April 30, 2015
    Inventors: Gilles A. Pokam, Cristiano L. Pereira
  • SEMICONDUCTOR DEVICE INCLUDING REPEATER CIRCUIT FOR MAIN DATA LINE
    Publication number: 20150120997
    Abstract: A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Inventors: SHINGO MITSUBORI, Hiroki Fujisawa
  • Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same
    Patent number: 9021176
    Abstract: A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David Resnick
  • Utilization of stored timing data to configure a memory controller
    Patent number: 9021193
    Abstract: A method for configuring a memory controller including determining whether a serial number of at least one memory module matches a stored serial number corresponding to at least one of the memory module and utilizing a stored timing data to configure the memory controller when the serial number matches the stored serial number corresponding to at least one of the memory module.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: April 28, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory Ziarnik, Jeffrey Kenline, Jose Sancho-Dominguez
  • SYSTEM-IN-PACKAGE MODULE WITH MEMORY
    Publication number: 20150113356
    Abstract: A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 23, 2015
    Inventors: Weng-Dah Ken, Chao-Chun Lu
  • Volatile memory device and memory controller
    Patent number: 9015389
    Abstract: A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Woong Lee, Hyong-Ryol Hwang
  • Load reduction dual in-line memory module (LRDIMM) and method for programming the same
    Patent number: 9015408
    Abstract: A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: April 21, 2015
    Assignee: Diablo Technologies, Inc.
    Inventors: Maher Amer, Michael Lewis Takefman
  • Autonomous memory subsystem architecture
    Patent number: 9015440
    Abstract: An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: April 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sean Eilert, Mark Leinwander, Jared Hulbert
  • METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE
    Publication number: 20150106560
    Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 16, 2015
    Inventors: Richard E. PEREGO, Pradeep BATRA, Steven WOO, Lawrence LAI, Chi-Ming YEUNG
  • Semiconductor memory systems with on-die data buffering
    Patent number: 9009400
    Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 14, 2015
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
  • Leveraging a hybrid infrastructure for dynamic memory allocation and persistent file storage
    Patent number: 9009392
    Abstract: Dynamic allocation of memory in a hybrid system is provided. In particular, a method and system is provided to leverage a hybrid infrastructure for dynamic memory allocation and persistent file storage. The method includes dynamically allocating a file or its part or to cache a file or its part between different storage technologies and respective memory technologies in a hybrid infrastructure.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bhushan P. Jain, Sandeep R. Patil, Sri Ramanathan, Gandhi Sivakumar, Matthew B. Trevathan
  • Dividing incoming data into multiple data streams and transforming the data for storage in a logical data object
    Patent number: 9003110
    Abstract: Various embodiments for storing a logical object are provided. In one such embodiment, by way of example only, incoming data is divided corresponding to a logical data object into a plurality of independent streams, associating each data chunk of a plurality of obtained data chunks with a corresponding stream among the plurality of independent streams. At least one of the obtained data chunks and derivatives thereof is sequentially accommodated in accordance with an order the obtained chunks are received, while keeping the association with the corresponding streams. A global index is generated as a single meta-data stream accommodated in the logical data object and comprising information common to the plurality of independent streams and related to mapping between data in the logical data object and the obtained data chunks.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Amit, Ori Shalev
  • MEMORY MANAGEMENT
    Publication number: 20150095563
    Abstract: Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventor: Robert J. Royer, JR.
  • APPARATUS AND METHOD FOR SELECTING MEMORY OUTSIDE A MEMORY ARRAY
    Publication number: 20150095564
    Abstract: An apparatus includes a memory module, which includes a memory array. The memory array includes rows of memory and columns of memory. The apparatus also includes at least one row of memory not in the memory array and a register. The register includes an address space and a row/column indicator. The apparatus also includes row selection logic to select the at least one row to be activated if the address from an address bus equals the register value and if the row/column indicator indicates row.
    Type: Application
    Filed: May 9, 2012
    Publication date: April 2, 2015
    Inventors: Melvin K. Benedict, Eric L. Pope, Guy E. McSwain, Joseph W. Fahy, Maurizio Contini
  • Method for addressing a memory card, a system using a memory card, and a memory card
    Patent number: RE45486
    Abstract: The present invention relates to a method for addressing the memory locations of a memory card. There are several memory locations in a memory card for storing data, in which case in order to address a specific memory location an address is formed. At least one parameter is stored in the memory card, on the basis of which parameter the number of memory locations of a memory card can be calculated, and a specific number of bits is reserved for said at least one parameter. In the method, two or more memory locations are addressed with one address, and/or the number of bits that can be used in an address is increased. The invention also relates to a system and a memory card in which the method is applied.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 21, 2015
    Assignee: Memory Technologies LLC
    Inventors: Marko Ahvenainen, Kimmo Mylly