Abstract: A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.

Abstract: A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer memory including volatile RAM and non-volatile RAM. The memory controller is configured to select one of the volatile RAM and the non-volatile RAM to temporally store the write data based on a write pattern of the write data, and to transmit a host command complete signal to a host when the write data is stored in the non-volatile RAM.

Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.

Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.

Abstract: According to an example, a counter policy implementation apparatus may include a policy determination module to receive a counter address for a local counter and to map the counter address to a specific policy of a plurality of policies, and a policy application module to receive a posted value and a double data rate (DDR) value associated with the local counter. The policy application module may include a comparator to compare the posted value or the DDR value with a maximum value associated with the local counter specified in the mapped policy, and an action block to perform an action specified by the mapped policy based on the comparison.

Abstract: A memory control system includes: a memory that stores data; a memory controller that controls operation of the memory by a memory control signal; and a CPU that forms a single link with the memory controller and transmits the memory control signal to the memory controller via the single link.

Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards.

Abstract: Systems and methods for timing read operations with a memory device are provided. A timing signal from the memory device is received at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating circuit is configured to open the gating window based on a control signal. The gating circuit is further configured to close the gating window based on a first edge of the timing signal. The first edge is determined based on a counter that is triggered to begin counting by the control signal. At a timing control circuit, the control signal is generated based on i) a count signal from the counter, and ii) a second edge of the timing signal that precedes the first edge in time.

Abstract: The present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to a hybrid storage system with a mid-plane. In a typical embodiment, a mid-plane is provided. Coupled to one side of the mid-plane is a system control board and a communications module having a set (at least one) of ports. Coupled to a second side of the mid-plane is (among other components) a first RAID controller, which itself is coupled to a double data rate semiconductor storage device (DDR SSD) module having a set of DDR SSD units. Also coupled to the second side of the mid-plane is a second RAID controller, which itself is coupled to a hard disk drive (HDD) module having a set of HDD/Flash SDD units.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

Abstract: A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.

Abstract: A method for storing data is disclosed, the method including collecting, by a CPU module, a source data and an RTC (Real Time Clock) value and storing the source data and the RTC value in a common RAM (Random Access Memory) of a data log module, converting, by an MPU (Micro Processing Unit) of the data log module, a type of the source data, and adding the RTC value and an index value to the converted value to generate a data row, and compressing, by a compression unit of the data log module, the generated data row, and storing the generated compressed data row in a memory card.

Abstract: A data processing apparatus includes bus masters and a memory controller. Each bus master includes a data buffer, and issues a memory command to specify access to the memory and generates first priority information depending on a free space of the data buffer, wherein the first priority information is associated with the memory command and indicates a priority of the memory command. The memory controller determines a processing order of memory commands which are issued by the plurality of bus masters based on the first priority information corresponding to the memory commands, and executes the respective memory commands transferred from the plurality of bus masters in the processing order determined by the processing order determining unit.

Abstract: A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory.

Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Abstract: A method, a statistics subsystem, and a system use a combination of commercially available high speed memory and high density low speed memory to mitigate cost, space, control, and power issues associated with storing counters for statistics updates, while meeting the growing width and depth needs of multi-hundred gigabit Carrier Class data network devices. The method, statistics subsystem, and system offer a Counter Management Algorithm (CMA) that relies on rollover bits stored within data of counters. An update to the low speed memory is substantially faster than a rollover time for the counter in the high speed memory thereby allowing statistics to be cached in the high speed memory while updates take place to the low speed memory.

Abstract: A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.

Abstract: A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface.

Abstract: A method can include receiving memory configuration information that specifies a memory configuration; receiving memory usage information for the memory configuration; analyzing the received memory usage information for a period of time; and, responsive to the analyzing, controlling notification circuitry configured to display a graphical user interface that presents information for physically altering a specified memory configuration. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.

Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract: Methods and structure are provided for maintaining gate training parameters for Random Access Memory. The system comprises a memory controller and a management unit. The management unit is able to initialize the system after the system returns from an unpowered state by accessing a non-volatile memory to retrieve timing intervals for electrical impulses sent between the memory controller and a Random Access Memory. The timing intervals previously enabled communication between the memory controller and the Random Access Memory. The management unit is further able to initialize the system after the system returns from an unpowered state by calibrating the memory controller to enable communication with the Random Access Memory based on the retrieved timing intervals.

Abstract: A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

Abstract: A semiconductor device may include a storage unit configured to store a number of times a first command has been provided to a memory cell array, a control unit configured to generate a second command operable to activate at least one word line in the memory cell array based on a comparison of the number stored at the storage unit with a threshold value, when the first command is received, and a selection unit configured to select one of the first command and the second command based on a result of the comparison and transmit the selected command to the memory cell array.

Abstract: Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.

Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.

Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.

Abstract: Current computer systems support sleep states such as sleep state S3 and sleep state S4. A system in sleep state S3 utilizes more power than one in sleep state S4, however, a system in sleep state S3 can resume function substantially faster than a system in sleep state S4. An idle system is often put into sleep state S3 rather than sleep state S4 because of the shorter resume time even though sleep state S3 utilizes more power. Embodiments include a reduced-power sleep state S3 that uses less power than sleep state S3 yet resumes function faster than sleep state S4. Embodiments reduce the power consumed by compressing and consolidating system context to fewer memory modules, and powering down unused memory modules. Embodiments thus avoid storing system content to non-volatile memory. Embodiments include waking the system by restoring system context in the reverse order to respective memory modules.

Abstract: Provided is a semiconductor device including: a plurality of processing circuits; an arbitration circuit that arbitrates a plurality of data transfer requests issued by the plurality of processing circuits; a mask control circuit that loads the plurality of data transfer requests arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period; and a memory controller that accesses a memory based on the plurality of data transfer requests sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period.

Abstract: Techniques for block storage using a hybrid memory device are described. In at least some embodiments, a hybrid memory device includes a volatile memory portion, such as dynamic random access memory (DRAM). The hybrid memory device further includes non-volatile memory portion, such as flash memory. In at least some embodiments, the hybrid memory device can be embodied as a non-volatile dual in-line memory module, or NVDIMM. Techniques discussed herein employ various functionalities to enable the hybrid memory device to be exposed to various entities as an available block storage device.

Abstract: A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.

Abstract: The present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to a switch-based hybrid storage system. In a typical embodiment, a first RAID controller is coupled to a system control board, and a double data rate semiconductor storage device (DDR SSD) module is coupled to the first RAID controller. The DDR SSD module typically includes a set of DDR SSD units. Also coupled to the system control board are a first switch and a second switch. A second RAID controller is coupled to the first switch, while a hard disk drive (HDD) module coupled to the second RAID controller. The HDD module typically includes a set of HDD/Flash SDD units. Also coupled to the second switch is a communications module having a set (at least one) of ports.

Abstract: The present invention is adapted to data storage technology field, and provides a reading/writing control method and system for nonvolatile memory, the method including the following steps: dividing valid blocks in the nonvolatile memory into different zones, the zones including at least one data zone having fixed number of valid blocks and one exchange zone having at least two valid blocks; creating a mapping table of logic blocks and physical blocks in each zone; establishing a mapping table of logic pages and physical pages in the blocks based on redundant area information of pages in the blocks, and storing the mapping table of the logic blocks and physical blocks in each zone and the mapping table of logic pages and physical pages in each block in a private data area; and writing data segments in an idle page of the blocks of the data zones in sequence, or reading data segments from valid pages in the data zones, thus the data reading/writing speed and efficiency is promoted.

Abstract: Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits.

Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.

Abstract: An operating access method for a DRAM is provided. A first address is obtained via an address bus and a first command is obtained via a command bus from a controller. A second address is obtained via the address bus and a second command is obtained via the command bus from the controller after the first command is obtained. The first address and the second address are combined to obtain a valid address, wherein the valid address is a row address when each of the first command and the second command is an active command. In addition, the valid address is a column address when the second command is an access command.

Abstract: An access method for a DRAM is provided. A row address is partitioned into a first portion and a second portion. The first portion of the row address is provided via an address bus and a first active command is provided via a command bus the DRAM. The second portion of the row address is provided via the address bus and a second active command is provided via the command bus to the DRAM, after the first active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address.

Abstract: A dedupe cache solution is provided that uses an in-line signature generation algorithm on the front-end of the data storage system and an off-line dedupe algorithm on the back-end of the data storage system. The in-line signature generation algorithm is performed as data is moved from the system memory device of the host system into the DRAM device of the storage controller. Because the signature generation algorithm is an in-line process, it has very little if any detrimental impact on write latency and is scalable to storage environments that have high IOPS. The back-end deduplication algorithm looks at data that the front-end process has indicated may be a duplicate and performs deduplication as needed. Because the deduplication algorithm is performed off-line on the back-end, it also does not contribute any additional write latency.

Abstract: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.

Abstract: In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.

Abstract: Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the read latency and/or the latency window of a memory controller such that a data signal and a data strobe signal are received by the memory controller within the latency window of the memory controller.

Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.