Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.

Abstract: Nonuniformities of luminance characteristics in a field emission display (FED) are compensated pixel by pixel by storing a matrix of correction values, determined by testing, and by applying a corrected drive signal through the relative column drive stages. The individual pixel's correction factor that is applied to the corresponding video signal may be stored in digital or analog form in a nonvolatile memory array. Various embodiments are described including the use of a second updatable RAM array wherein pixel's correction factors are calculated and stored at every power-on to provide an opportunity of trimming-up the luminance of the display for compensating long term decline of luminance due to the phosphors ageing process.

Abstract: Converter topologies in which two separate switching transistors and two capacitors are used on the input side. Preferably the two transistors are switched alternately, to alternately pull down different nodes in an inductor-capacitor chain. Two capacitors are interposed in series between an input inductor on the input and a transformer primary winding. Preferably the two transistors are connected with their parasitic diodes in opposite senses, so that one can source current from a first node to ground when off, and the other can sink current from a second node to ground when off.

Abstract: A reference voltage generator having a dual slope temperature characteristic, for use in an automotive alternator voltage regulator, comprises a bandgap circuit (R1,R2,R3,R4) which generates a voltage (A) having a thermal drift coefficient of zero and a voltage (B) having a non-zero thermal drift coefficient. These voltages are applied to a voltage divider (R5,R6) and a voltage-follower type of circuit (OPA1). A unidirectional conduction amplifier circuit (OPA2) has an input terminal connected to an intermediate point (C) on the voltage divider. A second voltage divider (R7,R8) is connected between the output terminals of the voltage-follower circuit (D) and the amplifier circuit (E) . An intermediate node (F) of the second voltage divider is coupled to an output terminal (VREF) of the generator.

Abstract: A rendering subsystem with enhanced capability for handling both 2D rendering and 3D rendering tasks. Since the 2D rendering tasks may be generated by the operating system (or other user-interfacing software), it is highly desirable not to interfere with rapid performance of 2D rendering, even if substantial 3D rendering tasks have been loaded into the pipeline. To avoid this, the innovative system uses dual independent contexts, and suspends 3D rendering operation during periods of 2D rendering demand. Moreover, a certain percentage of cycles is reserved, as a minimum, to be available for 2D operations if any have been requested. Window ownership identifiers are maintained for each pixel, but these identifiers are only updated when the 3D rendering operations have been suspended. Moreover, the window position (offset) values are only updated during periods when 3D rendering has been suspended.

Abstract: A low-voltage transconductor circuit in which the common mode gain of a first transconductor stage is compensated by a second transconductor stage (connected in parallel with the first transconductor stage) which has no differential mode transconductance, and which is connected so that its common mode transconductance offsets the common mode transconductance of the stage. This greatly reduces the common mode current signal at the output, while avoiding the necessity for a current sink at the source of the input transistors.

Abstract: A power conversion circuit, in which a flyback converter is modified with additional elements to provide both dissipationless snubbing and also input ripple cancellation. This is achieved by appropriate connection of an additional winding to the isolating transformer, without any need for a second transformer. The configuration of the secondary is conventional, and the switching transistor is connected in series with the primary winding across DC inputs (taken e.g. from a full-wave-rectified line voltage). The additional winding is connected on the primary side, and preferably has a near-unity turns ratio with the primary which is the inverse of the coupling coefficient. However, the additional winding is not connected between the two DC inputs, but instead has one end coupled through an intermediate capacitor to the corresponding end of the primary, and the other end coupled through a capacitor to the negative DC input.

Abstract: A method for the recognition of video standards, in which an up/down counter is used to detect the polarity of synchronization pulses. Specifically, a value representing a duration is memorized, a counting value (Q) is produced, this value being incremented when a binary synchronization signal (INCI) is in one state and decremented when this signal is in the other state, a comparison is made of the value representing the duration and the counting value, at a given time, of the synchronization signal, and a signal representing the standard is produced as a function of the result of the comparison. This method is implemented by a circuit comprising a microcontroller, a detection circuit producing a pick-up control logic signal (CAP), a counter producing a counting value (Q) and a register to load the counting value when the pick-up control signal is active.

Abstract: Electronic switch for low-voltage supply circuits completed with CMOS technology and comprising a first, a second and a third circuit element (SW1 ,SW2,SW3) consisting each of a pair of complementary transistors. The first and second of said elements (SW1,SW2) are inserted between two connection terminals of the switch (A,B) while the third element SW3 is inserted between a node (C) included between the first and the second element of a voltage reference (VCM). The first and second element are driven to conduction in phases (.phi.1) not overlapping the phases (.phi.2) in which it conducts the third element.

Abstract: A compatible interface for an installation to control household machines that comprises an omnibus line having at least two first line wires used for a supply current, information signals being transmitted on the two first wires and/or on two second line wires, wherein said interface comprises: a circuit to recognize whether information signals are sent on the two first wires or on the two second wires and to transmit a reception identification signal to a household machine; and a current regulation circuit connected to the two first wires to give a stabilized current supply even if information signals are transmitted on the two second wires. Applications include control of household (home automation), industrial, or professional installations.

Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults, such as low grain, in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

Abstract: A tool to aid in adjusting the position of a tandem rig under a trailer. The tool attaches to the tandem, where it can be adjusted to apply a force to the handle which unlocks the positioning pins. This allows adjustments to the position to be made without the need to walk back and check the tandem to see if the positioning pins have been freed from their locked position.

Abstract: Electrically programmable memories, in particular EPROMs, generally have an internal signature which can be read by the memory-programming device. This internal signature indicates the origin of the part (manufacturer's identification) and the appropriate programming mode for the part (fast programming, "intelligent" programming, etc.). Here, it is proposed that this information be recorded in a UPROM (unerasable programmable read-only) memory, i.e., in practice an EPROM memory masked by a layer of aluminium which prevents its erasure by ultraviolet rays.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: An integrated circuit memory that contains a device for the precharging and reading of the bit lines, including a precharging element, a current-voltage converter and a read circuit, further contains a test circuit to isolate the output of the converter from the precharging element and from the read circuit, to apply a test voltage to a cell of the memory through the converter and to measure the current in the cell.

Abstract: The invention relates to a shifter stage for a variable-length digital code decoder which decodes one code per clock cycle, reads input data arriving from a memory, supplies a logical unit on each cycle with a word having the size of the longest variable-length code to be decoded, receives from the logical unit the number of bits of the code decoded on the preceding clock cycle, and effects a shift in the data read equal to the cumulative total of the lengths of codes decoded since the last read of input data.It comprises a first barrel shift register (11) which reads the input data and performs a shift in the data read equal to the cumulative total of the lengths of the codes decoded between the preceding cycle and the start of the last read, and a second barrel shift register (13) which receives the data arriving from the first register and performs a shift equal to the length of the code decoded on the preceding cycle.

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

Abstract: In a switching converter that delivers power to a load, a transition between higher load and lower load modes is controlled by varying the width of switch control pulses in one operating phase and blanking individual pulses in another operating phase. Alternatively, in yet another operating phase the time interval between switch control pulses is varied and, at a given load condition, the time interval between successive pulses remains essentially constant.

Abstract: An arithmetic and logic computation device having an arithmetic and logic unit with a shifter on at least one input. The computation device, which includes a multiplier, propagates a carry and applies a carry to the multiplier to carry out double precision multiply and multiply-accumulate operations.

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor on a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the tint, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.