Patents Represented by Attorney Hayes Soloway P.C.
  • Patent number: 6587000
    Abstract: Current mirror circuit includes first constant current source, first and second MOS transistors, and first and second operational amplifiers. First constant current source outputs constant current to a first node based on a first reference voltage. First MOS transistor has source grounded, gate connected to the second MOS transistor and drain connected to the first node. Second MOS transistor has source grounded, gate connected to the first MOS transistor and drain connected to a second node. First operational amplifier has first input terminal connected to the first node, second input terminal connected to a third node connected to a second reference voltage and an output terminal connected to the gates of the first and second MOS transistors. Second operational amplifier has first input terminal connected to the third node, second input terminal connected to the second node and output terminal connected through feedback circuit to the second node.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: July 1, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Naoto Oikawa
  • Patent number: 6585937
    Abstract: A sample pre-separation and concentration system for detecting low levels of analytes in highly complex mixtures includes a plurality of trapping columns having a high selectivity for classes of compounds of interest, upstream of a standard separation column. The system may be used, for example, to measure urinary 8 hydroxy 2′ deoxyguanoisine.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: July 1, 2003
    Assignee: Esa, Inc.
    Inventor: Wayne R. Matson
  • Patent number: 6586674
    Abstract: A hermetically sealed housing for power electronics includes a sheet metal tank, and an aluminum cover. The tank has a surrounding edge which is provided with a plurality of bending lugs, and the edge of the cover has a shoulder at which the bending lug rests, so that the cover is pressed against the edge of the tank and a hermetic sealing is obtained.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: July 1, 2003
    Assignee: Harting Automotive GmbH & Co. KG
    Inventors: Jens Krause, Thomas Heimann
  • Patent number: 6584371
    Abstract: A lot-base management host computer performs management of wafers with a lot as a unit by managing a process condition for each lot, a correspondence between a carrier ID and a lot ID, and a correspondence between a slot ID and a wafer ID in each lot. A wafer-base management host computer performs management for each wafer in a lot by managing a process condition corresponding to a wafer number in a lot. Further, a converted condition instructing section transmits data acquired from the lot-base management host computer and the wafer-base management host computer to a semiconductor fabrication apparatus. The wafer-base management host computer stores a process condition for each level and a machine number of a semiconductor fabrication apparatus in use in the form of a matrix as an experimental level master and issues a process condition as instructions to the semiconductor fabrication apparatus through the converted condition instructing section according to the experimental level master.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: June 24, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Toshihiro Sada, Junji Orimoto
  • Patent number: 6584607
    Abstract: A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. (a) An initial layout result is generated through placement of functional blocks of the circuit and routing of wiring lines therefor. (b) Wiring capacitance values of the respective blocks are calculated using the initial layout result. (c) Fan-out capacitance limitation values of the respective blocks are calculated using the wiring capacitance values of the blocks. Each of the fan-out capacitance limitation values represents a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value. (d) A driving capability of each of the blocks is compared with its fan-out capacitance limitation value, thereby generating a comparison result.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: June 24, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Kazuyuki Irie
  • Patent number: 6584332
    Abstract: An electronic equipment includes one or more electronic devices, a cold stage, and a cold insulation member. The one or more electronic devices perform a predetermined operation within a predetermined temperature range. The cold stage cools down the one or more electronic devices to a predetermined operational temperature at which the one or more electronic devices is operable. The phase transition temperature of the cold insulation member is in a range between the predetermined operational temperature and an upper limit of the predetermined temperature range. The cold insulation member is arranged adjacent to the one or more electronic devices, and retains the temperature of the one or more electronic devices within the predetermined temperature range. At least one electronic devices over which the cold insulation member is arranged is partially formed from a material which is in a superconductive state at the predetermined operational temperature.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: June 24, 2003
    Assignee: NEC Corporation
    Inventors: Tsutomu Yoshitake, Wataru Hattori
  • Patent number: 6580492
    Abstract: A reticle system includes a reticle film having thereon a plurality of scale patterns each having a plurality of scale marks plotted therein, and a shield film having a plurality of pinholes each disposed corresponding to one of the scale patterns. A light emitted from a point light source having an effective coherent factor “x” and passing the reticle film at a scale mark “x” or below “x” in one of the scale patterns passes through the corresponding pinhole. After transferring the scale patterns onto a wafer surface, the effective coherent factors are read from the maximum scale marks for respective scale patterns on the wafer surface. The dispersion of the coherent factors can be calculated therefrom.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: June 17, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Masashi Fujimoto
  • Patent number: 6579477
    Abstract: A method for fabricating optical components by replication using a matrix, and optical components obtained by such method are described. The optical components are diffractive optical components, such as light-diffraction networks which are used in optical devices in order to divert a light beam according to a preferential order of diffraction.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: June 17, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Philippe Belleville, Philippe Gacoin, Sophie Kaladgew
  • Patent number: 6579346
    Abstract: A pressure swing adsorption process wherein a constant flow of feed gas and product gas is maintained to and from a pressure swing adsorption installation. A part of repressurization is carried out by a product gas split-off, in three stages, with an additional pressure equilibration step between two adsorbers during the second of the three stages, thereby cyclically fluctuating one of the number of adsorbers receiving feed gas during some period. In addition, either combined herewith or not, in case of the use of a higher purge gas pressure, is the return to a regenerated adsorber of a least impure part of the offgas, driven by its initially higher pressure. The result is an increased product recovery efficiency and an improved flexibility of functioning of the installation.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: June 17, 2003
    Assignee: Esselink BV
    Inventor: Abraham Johan Esselink
  • Patent number: 6580486
    Abstract: Disclosed is an active matrix liquid crystal display device, comprising: a pixel matrix; a data driver circuit for driving data lines; and gate driver circuits for driving gate lines. These constituting elements are all manufactured on the same substrate, and the data driver circuit and the gate driver circuits are formed outside a sealing region located outside the pixel matrix. In this case, all data lines formed between the data driver circuit and the pixel matrix are substantially covered by at least one metal layer which is composed of a metal different from that of the data lines, wherein the metal layer is adapted to perform both light shielding and reduction of electrostatic coupling capacitance between the data lines. Thus, it is possible to improve image quality by reducing noise generated following voltage fluctuation between data lines without providing any new metal layers for shielding.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: June 17, 2003
    Assignee: NEC Corporation
    Inventor: Hiroyuki Sekine
  • Patent number: 6577167
    Abstract: A clock signal producing apparatus is composed of a detecting circuit and a clock signal outputting circuit. The detecting circuit detects edge timings of an input signal at which the input signal is inverted. The edge timings are quantized to a predetermined number of states. A clock signal outputting circuit outputs an outputted clock signal. A phase of the outputted clock signal is adjusted based on the edge timings.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 10, 2003
    Assignee: NEC Corporation
    Inventor: Masaaki Soda
  • Patent number: 6574036
    Abstract: An optical process for the programmable time profile shaping of quasi-monochromatic optical pulses, involves the following steps: (1) spectral components of a wide spectrum pulse are spread out over time, and a stretched pulse with frequency drift is obtained, while conserving spectral width; (2) the pulse is spectrally shaped and, as a consequence, time shaped; and (3) the wide spectrum is converted into a narrow spectrum, while conserving time shaping.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: June 3, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Fabrice Raoult, Daniel Husson, Claude Rouyer, Christian Sauteret, Arnold Migus
  • Patent number: 6573106
    Abstract: A method of pre-treating carbon or graphite material to increase porosity and render pore size more uniform includes etching by electrochemically pulsing the material in an acid saline solution and optionally steam treating.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: June 3, 2003
    Assignee: Esa, Inc.
    Inventor: Wayne R. Matson
  • Patent number: 6573969
    Abstract: An active matrix type liquid crystal display includes an array of pixels each implemented by a combination of a thin film transistor, a pixel electrode connected through the thin film transistor to a signal line, a common electrode spaced from said pixel electrode and liquid crystal filling the gap between the pixel electrode and the common electrode, and spacers are inserted between a protective insulating layer over back channel regions of the thin film transistors and a planarization layer, wherein the spacers are conductive and fixed to a certain potential level in such a manner as to eliminate the conductivity from the back channel regions.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: June 3, 2003
    Assignee: NEC Corporation
    Inventors: Makoto Watanabe, Shoichi Kuroha, Masanobu Hidehira
  • Patent number: 6574169
    Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the test clock signal in the test mode.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: June 3, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Hisashi Yamauchi
  • Patent number: 6574258
    Abstract: A semiconductor laser, optical module using a semiconductor laser, and optical communication system using a semiconductor laser. The semiconductor laser has an active layer between two semiconductor layers and different conduction types and current block layers surrounding the active layer. One of the semiconductor layers has a first growth layer and a second growth layer formed on the first growth layer by a re-growth process after a growth process for the first growth layer. The doping concentration of the first growth layer, in the region of the interface with the second growth layer, is in the range of between 1.5 to 5 times the doping concentration of the second growth layer.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: June 3, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Hiroyuki Yamazaki
  • Patent number: 6570744
    Abstract: A magnetic layer which is exchange-coupled to an antiferromagnetic layer and given an exchange bias therefrom is laminated via a non-magnetic layer on another magnetic layer to form an MR film. The antiferromagnetic layer (PtMn, PdMn or NiMn) is laminated on a ground layer(Zr, Hf, Zr—Hf, Zr—Co, Zr—Au, Ni—O, Co—O or Fe—O) so that the antiferromagnetic layer has a surface of an average roughness of 1-5 Å. A conduction layer is formed adjacent to the magnetic layer for sensing a magnetic field. The conduction layer is made of Cu, Ag, Au or an alloy composed of two selected therefrom. A layer made of Zr, Ta, Zr—O, Ta—O or a mixture thereof is laminated on the conduction layer. The MR film exhibits a large resistance variation linearly at near zero magnetic field with an excellent thermal stability.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: May 27, 2003
    Assignee: TDK Corporation
    Inventors: Junichi Fujikata, Masafumi Nakada
  • Patent number: D476312
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: June 24, 2003
    Assignee: Brookstone Company, Inc.
    Inventors: David Harris, Rudy Woodard, Tim Trzepacz
  • Patent number: D476579
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: July 1, 2003
    Assignee: Brookstone Company, Inc.
    Inventors: David Harris, Rudy Woodard, Greg Froton, Baird Little
  • Patent number: D476640
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: July 1, 2003
    Assignee: Brookstone Company, Inc.
    Inventors: David Harris, Rudy Woodard, Tim Trzepacz