Abstract: An interterminal anti-short-circuiting pattern is formed in an upper metal wire included in a connection terminal 3, for connecting to external driving LSI and the like, located on the projected portion of a bottom glass substrate 2. This pattern includes recess 4 and island 5 on which a contact hole 12a is formed through a protective insulating film. The protective insulating film has high residence to water penetration. Spread of the corrosion can be shut off by the recess surrounding the island. Short circuit occurrence due to interterminal current leak can be inhibited under high moisture conditions in the semiconductor device used for active matrix display, e.g. LCD panel.

Abstract: Sustaining discharges are conducted in a first sub-field in a pair of adjacent first and second sub-fields. Then, writing discharges in a second sub-field are conducted after the sustaining discharges in the first sub-field without conducting any erasure discharge between the sustaining discharges and the writing discharges. A relation expressed by an equation L1=L2=1 and an inequality Ln+2≦Ln+1+Ln holds for a luminance weighting Li. The luminance weighting Li is a luminance weighting of the i-th lowest sub-field from the bottom among the plurality of sub-fields.

Abstract: A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N×k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.

Abstract: This invention relates to a method for conditioning a waste constituted of an aqueous solution of sodium hydroxide NaOH of 3 to 10 M, possibly radioactive. The method is as follows: a) a metakaolin powder is added to the aqueous solution such that a suspension is obtained capable of solidifying and forming a crystalline phase of the zeolite A type; b) the suspension is introduced into a mould; c) the suspension is left to solidify in the mould in order to obtain a moulded solid product based on zeolite A; d) the moulded product is dried; and e) the zeolite A phase is converted into a nepheline type phase by heat treatment at a temperature of 1000° C. to 1500° C.

Abstract: The present invention provides a resin-molding method comprising the steps of: placing a circuit base member onto a mounting face of first one of paired dies, wherein a back face of the circuit base member is in contact with the mounting face; placing the paired dies in a closing state for clamping a peripheral region of the circuit base member with the paired dies; and injecting a molten resin into a cavity of the paired dies for filling the cavity with the injected resin, wherein, in the closing state, a first pressure effected to a front face of the circuit base member is set higher in pressure level than a second pressure effected to the back face of the circuit base member, so as to secure the circuit base member to the mounting face.

Abstract: An output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, includes (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line. The second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply.

Abstract: A belt-shaped sealant is coated on a substrate to surround a periphery of a display region of a flat type display device. A start point and a termination point of the sealant are disposed remote from the display region such that the sealant never intrudes into the inside of the display region when the sealant is pressed between opposing substrates of the display device.

Abstract: A protective circuit includes a floating gate MOSFET having a source-drain path connected between an I/O line and a source line or a ground line, a control gate connected to the I/O line and a floating gate connected to the source line or the ground line.

Abstract: A doubled wall container is disclosed having a fill cap that allows a user to alternately add or remove a liquid from an interior volume formed between the walls of the container.

Abstract: A first magnetic layer (3) is laminated on a magnetic yoke film (2) forming a closed magnetic circuit containing a magnetic gap so as to be magnetically coupled to the magnetic yoke film (2), and a magnetic separation layer (4), a second magnetic layer (5) and an antiferromagnetic layer (6) are laminated on the first magnetic layer (3). Further, a pair of electrodes (1, 7) are formed so that the laminate comprising the above layers is sandwiched between the electrodes. A permanent magnet film 8 is disposed to apply a bias magnetic field to the first magnetic layer (3). The magnetic separation layer (4) is formed of an insulator.

Abstract: A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.

Abstract: A liquid crystal display device having a switching device with a first electrode connected to the scanning line to become a gate, a second electrode connected to the signal line to become a drain or a source, a third electrode connected to the pixel electrode to become the source or the drain and switching the display signal to feed the corresponding pixel electrode by the scanning signal; and an electrode for an auxiliary capacitor, located in a place opposite to the pixel electrode to define the auxiliary capacitor. Further, the second and third electrodes are formed in a layer different from the first electrode, the pixel electrode is formed in top of the first, second, and third electrodes, and the electrode for an auxiliary capacitor is formed on the same layer as the first electrode.

Abstract: A semiconductor apparatus comprising: a semiconductor substrate; a first surface of the semiconductor substrate on which a semiconductor device is formed; a second surface opposite to the first surface of the semiconductor substrate; a via hole penetrating through the semiconductor substrate from the first surface to second surface; an electrode, provided on the second surface, connecting to the via hole; wherein the electrode having a barrier layer for preventing any diffusion of a soldering material into the via hole.

Abstract: A method is disclosed for producing a transgenic plant with a modified inulin producing profile comprising in its genome a combination of one or more expressible 1-SST enzyme encoding genes and one or more expressible 1-FFT enzyme encoding genes, wherein either of these genes or both of them comprise one or more recombinant genes containing one or more 1-SST, respectively 1-FFT, enzyme encoding DNA sequences of plant origin or an expressible homologous sequence thereof. The invention also relates to a method for modifying and controlling the inulin profile of plants and to a method for producing inulin from said transgenic plants. Furthermore, a novel cDNA sequence of a 1-SST enzyme encoding gene of Helianthus tuberosus and a novel cDNA sequence of a 1-FFT enzyme encoding gene of Cichorium intybus are disclosed, novel recombinant DNA constructs and genes derived thereof, as well as novel combinations of expressible 1-SST and 1-FFT enzyme encoding genes.

Abstract: A LCD device includes a pair of phase compensating plates for controlling the overall retardation of the LCD device substantially at a constant between the substrates. A wavelength-dependent compensating plate is additionally provided for compensating the wavelength dependency of the overall retardation of the LCD device to improve the contrast ratio.

Abstract: A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.

Abstract: A phase change optical disk has a multilayered structure obtained by sequentially forming at least a lower dielectric layer, recording layer, upper dielectric layer, and reflective layer on a substrate. The reflectance Rc of the disk with respect to light with a wavelength of 380 nm to 430 nm, when the recording layer is in a crystalline state, is lower than the reflectance Ra of the disk when the recording layer is in an amorphous state.

Abstract: A printing configuration utility provides a single test sheet. The single test sheet is printed twice. The first printing has a first location mark capable of indicating orientation of the first project. The second printing has a second location mark capable of indicating orientation of the second project. After performing the first printing on the test sheet, the printing utility provides the user with instructions for reinserting the test sheet for the second printing. The printing utility asks questions to the user about the first and second printings including the relation between the first and second location marks. Based on the answers given by the user, the printing utility determines the orientation of pages when they are reinserted for the printing the second sides of the pages, and the order of processing of the second side printing.