Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.

Abstract: A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n?1) have an error.

Abstract: A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode.

Abstract: A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.

Abstract: A method and apparatus controls power consumption of stations having a hierarchical structure when the stations transmit and receive a wireless signal to and from one another on a CSMA/CA wireless LAN. The controlling involves extracting information on frame transmission speed and transmission period information on first and second layers of the hierarchical structure from the wireless signal; determining a power-controlled period for each of the first and second layers based on the extracted information; and reducing the power consumption of the first and second layers by switching a current mode of the first and second layers to a predetermined mode for the power-controlled period if a reception address included in the extracted information is not identical to an address of the station.

Abstract: A protective layer of a plasma display panel includes smoky magnesium oxide, the smoky magnesium oxide having single crystal magnesium oxide with a plurality of cavities therein.

Abstract: A method of manufacturing a display device, including providing a composition including a conductive material, an organic binder; a glass frit, and a solvent, wherein the organic binder has a glass transition temperature of about ?50° C. to about ?5° C., loading the composition into grooves of a gravure roll, transferring the composition from the grooves of the gravure roll onto a silicone rubber blanket roll, transferring the composition from the blanket roll onto a glass substrate, and drying and firing the composition transferred on the glass substrate to form an electrode.

Abstract: A method of manufacturing a semiconductor device includes preparing a substrate on which a fuze line containing copper is formed. The method further includes cutting the fuze line by emitting a laser beam, and applying a composition for etching copper to the substrate to finely etch a cutting area of the fuze line and to substantially remove at least one of a copper residue and a copper oxide residue remaining near the cutting area. The composition for etching copper includes about 0.01 to about 10 percent by weight of an organic acid, about 0.01 to 1.0 percent by weight of an oxidizing agent, and a protic solvent.

Abstract: A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.

Abstract: Exemplary embodiments relate to a substrate testing device having a comparator adapted to compare a power supply voltage supplied by a power supply voltage line with a dropped power supply voltage detected by a power supply voltage detection line and to output a voltage difference, and a level shifter circuit adapted to compensate a data voltage with a voltage up to an amount equal to the voltage difference output from the comparator and to supply the data voltage to a display panel.

Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

Abstract: An electrode assembly for a rechargeable battery resists external impacts applied to the rechargeable battery, and includes a sealing tape attached to an outer circumference of the rechargeable battery, which extends toward an upper part and a lower part to prevent the electrode assembly from unfastening, and a top insulating plate and a bottom insulating plate may be attached to the extended portion of the sealing tape. A shock resistant electrode assembly for a rechargeable battery has an insulating plate attached thereto by an extended portion of a sealing tape, thereby preventing the electrode assembly from moving in a battery housing when an external impact is applied.

Abstract: An organic light-emitting device, including a substrate, an organic light-emitting element on the substrate, a sealing member on the organic light-emitting element, a ¼ wavelength layer on one surface of the substrate, the organic light-emitting element, or the sealing member, and a linear polarization layer on one surface of the substrate, the organic light-emitting element, the sealing member, or the ¼ wavelength layer, the linear polarization layer being closer to an image display surface than the ¼ wavelength layer.

Abstract: A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.

Abstract: A metal catalyst including a conductive catalyst material and a coating layer formed of a water repellent material on the conductive catalyst material, an electrode including the metal catalyst, and a fuel cell employing the electrode. By forming the coating layer, having a water repellent material, on the conductive catalyst material, the metal catalyst does not sink in the liquid electrolyte, the distribution and movement of the liquid electrolyte around the metal catalyst can be controlled, and the thickness of the interface between the metal catalyst and the liquid electrolyte can be regulated. Accordingly, an ideal electrode structure having triple phase boundary for electrochemical reaction can be formed. A fuel cell employing an electrode including the metal catalyst has excellent efficiency and overall performance.

Abstract: A data driving circuit for a light emitting display may include a gamma voltage generator that generates gradation voltages, a current sink that receives a predetermined current from a pixel via a data line during a first partial period of one complete period for driving the pixel, a voltage generator that generates an incrementally increasing compare voltage during the first partial period, a comparator that compares a compensation voltage generated based on the predetermined current with the compare voltage and generates a logic signal based on a result of the compare, an adjusting unit that generates compensation data based on the logic signal, and a digital-analog converter that generates a composite data using the compensation data and externally supplied data and selects, as a data signal for the pixel, one of the plurality of gradation voltages based on a bit value of the composite data.

Abstract: A method of fabricating a photomask may include forming a light-shielding layer and a first resist film on a substrate, forming a first resist pattern by exposing first exposed regions of the first resist film to a first exposure source that may have a first energy, forming a first light shielding pattern by etching the selectively exposed light-shielding layer by using the first resist pattern as an etching mask, removing the first resist pattern, forming a second resist film on the first light-shielding layer, exposing second exposed regions of the second resist film that may have a desired pattern shape to a second exposure source that may have a second energy, forming a second light shielding pattern by etching the selectively exposed first light shielding pattern by using the second resist pattern as an etching mask, and removing the second resist pattern.

Abstract: A polymer electrolyte membrane includes a cross-linking reaction product between a hydrophilic polymer and a cross-linking agent represented by Formula 1 below wherein R1 is substituted or unsubstituted C1-C20 alkyl group, substituted or unsubstituted C6-C20 aryl group, or substituted or unsubstituted C2-C20 heteroaryl group; and n is an integer in the range of 1 to 5. The polymer electrolyte membrane may be prepared by preparing a composition for forming a polymer electrolyte membrane including the hydrophilic polymer, the cross-linking agent represented by Formula 1 and a solvent, applying the composition for forming a polymer electrolyte membrane to a supporting substrate; and heat treating the composition for forming the polymer electrolyte membrane to form the polymer electrolyte membrane. A fuel cell or other device includes the polymer electrolyte membrane. The polymer electrolyte membrane has low solubility to a strong acid and excellent ionic conductivity.

Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

Abstract: A direct methanol fuel cell (DMFC) comprising: a membrane electrode assembly (MEA) including an anode, a cathode, and a membrane disposed therebetween; a spacer surrounding the anode, having supply holes to supply methanol to the anode; and a flow control member to control the supply of the methanol. The flow control member includes a porous support and/or a methanol transmissive layer. The methanol transmissive layer comprises a fluorine polymer, a hydrocarbon polymer, or a combination thereof.