Abstract: A plasma display panel includes a first and second substrates disposed facing each other, an address electrode formed on the first substrate and extending in a first direction, a first dielectric layer covering the address electrode, a second dielectric layer on the first dielectric layer, a first electrode and a second electrode alternately disposed on the second dielectric layer and extending in a second direction, a third dielectric layer covering the first electrode and the second electrode, a discharge space, the discharge space having a bottom defined by the first dielectric layer at a bottom of the discharge space and sidewalls defined by the second and third dielectric layers, and a phosphor layer in the discharge space.

Abstract: An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal clock signal and to output a lock failure signal in response thereto, a duty cycle correction unit configured to correct a duty cycle of an external clock signal responsive to the lock failure signal and to output the duty-cycle-corrected external clock signal as the first internal clock signal, and a delay unit configured to generate the second internal clock signal by delaying the first internal clock signal.

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract: A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.

Abstract: An ambulatory robot including a lower body part having two or more legs and an upper body part installed on an upper end of the lower body part and capable of performing positional displacement by moving the lower body part, includes slope-detection means for sensing a slope of a floor, rotating means installed on a bottom surface of each of the two or more legs, and control means for controlling a motion of the ambulatory robot using the lower and upper body parts, wherein the control means controls a speed of revolution of the rotating means based on the slope of the floor, and controls the motion of the ambulatory robot so that the positional displacement of the ambulatory robot is performed by any of running, walking and sliding, depending on the controlled speed of revolution.

Abstract: A nanodot material including nanodots formed on silicon oxide, and a method of manufacturing the same, is provided. The nanodot material includes a substrate, a silicon oxide layer, and a plurality of nanodots on the silicon oxide layer.

Abstract: A plasma display panel plasma display panel includes a first substrate, a second substrate facing the first substrate, address electrodes between the first and second substrates, barrier ribs between the first and the second substrates, the barrier ribs defining discharge cells, phosphor in each discharge cell and first and second opaque electrodes between the first and second substrates, the first and second opaque electrodes extending orthogonally to the address electrodes. Each opaque electrode includes a first layer and a second layer, the first layer being narrower than the second layer. Each discharge cell is between a corresponding address electrode on a first side and a corresponding pair of first and second opaque electrodes on a second side, opposite the first side.

Abstract: A non-volatile memory device includes a buffer oxide film on a substrate; a polysilicon layer on the buffer oxide film; a silicon oxy-nitride (SiON) layer on the polysilicon layer, a first insulator layer on the SiON layer, a nitride film on the first insulator, a second insulator layer on the nitride film, an electrode on the second insulator, and a source/drain in the polysilicon layer.

Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

Abstract: A plasma display panel having improved bus electrode layer structure helps to prevent defective non-discharging discharge cells. From the overlapped transparent electrode layer and the bus electrode layer of the plasma display panel, protrusions extend from respective line portions towards a center of corresponding discharge cells. The protrusions of the transparent electrode layer are longer in length than the protrusions of the bus electrode layer. The width of the bus electrode layer is wider than the base of the protrusion of the transparent electrode layer and provides electrical connectivity even when the base of the protrusion of the transparent electrode layer breaks.

Abstract: In a method for forming a photoresist pattern, a method for forming a capacitor, and a capacitor manufactured using the same, a light is selectively irradiated onto a selected portion of a photoresist film formed on a substrate. An interfered light generated from the irradiated light is transmitted through other portions of the photoresist film except a ring-shaped portion of the photoresist film having a predetermined width along a boundary of the selected portion. The photoresist film is exposed using the interfered light and the light irradiated onto the selected portion. A cylindrical photoresist pattern having a minute width may be formed through developing the photoresist film. With the cylindrical pattern, the capacitor can be easily formed.

Abstract: Optoelectronic devices are provided that incorporate quantum dots as the electroluminescent layer in an inorganic wide-bandgap heterostructure. The quantum dots serve as the optically active component of the device and, in multilayer quantum dot embodiments, facilitate nanoscale epitaxial lateral overgrowth (NELOG) in heterostructures having non-lattice matched substrates. The quantum dots in such devices will be electrically pumped and exhibit electroluminescence, as opposed to being optically pumped and exhibiting photoluminescence. There is no inherent “Stokes loss” in electroluminescence thus the devices of the present invention have potentially higher efficiency than optically pumped quantum dot devices. Devices resulting from the present invention are capable of providing deep green visible light, as well as, any other color in the visible spectrum, including white light by blending different sizes and compositions of the dots and controlling manufacturing processes.

Abstract: A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduce, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.

Abstract: A plasma display module including a plasma display panel (PDP) including a first substrate and a second substrate and having an alignment mark formed thereon, and a chassis supporting the PDP and having an alignment mark corresponding to the alignment mark of the PDP.

Abstract: A piezoelectric inkjet printhead including a reversible shutter disposed in an ink flow path is disclosed. The inkjet printhead may includes a plurality of ink pressure chambers, a plurality of piezoelectric actuators to provide the plurality of ink pressure chambers with a driving force for ink ejection, an ink manifold to supply the plurality of pressure chambers, a plurality of restrictors disposed in the ink flow path between the manifold and the plurality of pressure chambers, a plurality of ink ejecting nozzles coupled to the plurality of pressure chambers, and a plurality of unidirectional shutters. The shutters may be disposed at respective outlets of the plurality of restrictors and may be adapted to open the restrictor when ink is supplied from the restrictor to the pressure chamber and close the restrictor and restrict or prevent the backflow of ink when ink is ejected from the pressure chamber through the nozzle.

Abstract: A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.

Abstract: A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.

Abstract: A cylindrical battery including a wound electrode assembly and a center pin disposed in a center space of the electrode assembly, the center pin having a gap along its length, the gap defined by opposing edges of the center pin, wherein at least one of the opposing edges is sloped.

Abstract: A power supply that is employable by a plasma display device for generating and supplying a plurality of voltages, the power supply including a first power source generating and supplying a first voltage, a transistor having a drain electrically coupled to the first power source, a first resistor having a first end coupled to the first power source and a second end electrically coupled to a gate of the transistor, a second resistor having a first end coupled to the second end of the first resistor and a second end electrically coupled to a second power source supplying a second voltage that is lower than the first voltage, and a capacitor having a first end coupled to a source of the transistor and a second end electrically coupled to the second power source. The coupling of the first end of the capacitor to the source of the transistor may form a third voltage supply node having the third voltage when the capacitor is charged.

Abstract: A plasma display panel includes a first substrate, a second substrate separated from the first substrate by a predetermined distance, a plurality of discharge cells in which a discharge occurs, the discharge cells being between the first and second substrate, and a plurality of pairs of sustain electrodes disposed between the first substrate and the second substrate and generating a discharge, wherein each sustain electrode includes a plurality of electrode portions and connection portions electrically connecting the electrode portions, and line widths of the connection portions corresponding to the discharge cells having the highest brightness among the red, green, and blue discharge cells are smaller than line widths of the connection portions corresponding to other discharge cells.