Abstract: A step motor control circuit that does not fix a reference voltage of a step motor control signal. The step motor control circuit may include a digital-to-analog (DAC) signal generator configured to generate first and second DAC signals in response to a step motor error signal, a gain adjust block configured to control gains of the first and second DAC signals in response to a control signal and output first and second step motor control signals, and a gain controller configured to output the control signal in response to a mode signal and a gain control signal, in which the first and second step motor control signals are pulse trains including a reference voltage, and the reference voltage may be a fixed voltage when the mode signal indicates a normal mode and the reference voltage may be a variable voltage when the mode signal indicates a power consumption reduction mode.

Abstract: A semiconductor device having superior capacitance may include interconnections formed on a semiconductor substrate, an interlayer insulation layer on the interconnections and having vias exposing a portion of the top surface of the interconnections, a capacitor which may be on the interlayer insulation layer and having a bottom electrode, a dielectric layer pattern, and a top electrode which may be sequentially stacked, and a pad structure may be connected to the interconnections through the vias. The pad structure may include pads for bonding with external electronic devices and a first upper interconnection connected to the top electrode of the capacitor.

Abstract: A piezoelectric inkjet printhead, and a method of manufacturing the same, includes an ink inlet for allowing inflow of ink, a plurality of pressure chambers to contain ink to be ejected, the plurality of pressure chambers being in communication with the ink inlet, a manifold formed in communication with the ink inlet, a plurality of restrictors connecting the manifold to respective first ends of the pressure chambers, a plurality of dampers at positions corresponding to respective second ends of the pressure chambers, the second ends being opposite the first ends, a plurality of nozzles in communication with the plurality of dampers for ejecting the ink, a plurality of actuators for applying a driving force to each of the pressure chambers for ejecting the ink, a damping membrane under the manifold for dampening a pressure change inside the manifold and a cavity under the damping membrane.

Abstract: An electron emission device that includes a substrate, at least one electron emission region, and at least one cathode electrode disposed on the substrate and electrically connected to the electron emission region, wherein the cathode electrode has a first electrode, a plurality of second electrodes on the first electrode, a sub-insulation layer between the first and second electrodes, and a resistive layer electrically connected to the first and second electrodes.

Abstract: A logic gate includes a first driver connected to a first power source, a first control transistor connected between a first node and a second power source to control a voltage of the first node, a second driver connected between a gate electrode of the first control transistor and the second power source, a third driver connected between the first power source and the second power source, a second control transistor connected between the third driver and the second power source, and having a first electrode connected to an output terminal, and a fourth driver arranged between a gate electrode of the second control transistor and the second power source, wherein the first control transistor, the second control transistor and each transistor of the first driver, the second driver, the third driver and the fourth driver are PMOS transistors.

Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.

Abstract: A plasma display module including a plasma display panel having front and rear surfaces, a chassis base made of a synthetic resin, having mounting holes formed therein, and being mounted on the rear surface of the plasma display panel, a heat conductive sheet disposed between the plasma display panel and the chassis base, a plurality of driving boards being mounted on a rear surface of the chassis base, the driving boards having a plurality of circuits connected to the plasma display panel by means of signal lines, and a plurality of gap pads mounted in the mounting holes formed in the chassis base to transfer heat generated from the driving boards to the heat conductive sheet, thereby discharging the heat.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

Abstract: An encryption method for encrypting data for multi-level access control in an ad-hoc network including hierarchical security classes includes encoding data into a predetermined code using a first public key of a highest security class, adding a private key of a security class to which a user belongs, to the predetermined code, and generating a ciphertext by adding a second public key, published by the security class to which the user belongs, to the addition result. A corresponding decryption method includes subtracting the private key from the ciphertext, performing a first decoding using a secret key known by a security class, to which a receiver belongs, by the receiver of the ciphertext, and correcting errors included in the second public key and detecting the data by performing a second decoding of the result of the first decoding using a code known by the security class to which the receiver belongs.

Abstract: An image sensor includes at least one photoelectric conversion area on a semiconductor substrate, a color filter over the photoelectric conversion area, and an apochromatic microlens over the color filter.

Abstract: An optical element may include a first diffractive structure having a radially symmetric amplitude function and a second diffractive structure having a phase function. The second diffractive structure may serve as a vortex lens. A system employing the optical element may include a light source and/or a detector.

Abstract: A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.

Abstract: A multi-threshold CMOS system and method controls a state of respective blocks individually. Each block includes a logic circuit having a logic transistor and a control transistor connected between the logic circuit and a power line connected to one of a ground and a power source. The control transistor has a higher threshold than the logic transistor. The blocks are controlled by generating an individual block ON/OFF signal for each block, generating an individual control signal in response to the individual block ON/OFF signal, supplying the individual control signal to the control transistor and controlling voltage supply to the logic circuit within each block in accordance with the individual control signal.

Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.

Abstract: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

Abstract: A light guide member for guiding light received from a light source, the light source illuminating light toward the light guide member, the light guide member may include a plurality of first grooves on a first side of the light guide member, the first grooves extending along a first direction crossing a zero-degree radiation angle of the light from the light source, wherein an angle of a reflective face of the first groove increases approaching away from the light source of the light source.

Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.

Abstract: A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a first charge blocking layer on the charge trapping layer by supplying a metal source gas and a first oxidizing gas onto the charge trapping layer, forming a second charge blocking layer on the first charge blocking layer by supplying a metal source gas and a second oxidizing gas onto the first charge blocking layer, wherein the second oxidizing gas has a higher oxidizing power as compared to the first oxidizing gas, and forming a gate electrode layer on the second charge blocking layer.

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) structure having a cylindrical shape. Elements of the MTJ structure are co-axial. The MTJ structure includes a conductive layer, an insulating layer co-axially formed around the conductive layer and a material layer formed around the insulating layer, the material layer being co-axial with the conductive layer and having a plurality of magnetic layers. The material layer includes a lower magnetic layer, a tunneling layer, and an upper magnetic layer that are sequentially stacked around and along the conductive layer.