Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: A positive photoresist composition having improved sensitivity and resolution, a method of making the composition, and a method for forming a pattern during semiconductor processing using the composition are disclosed. The photoresist composition includes: (i) a photosensitive material obtained by mixing a first photosensitive compound represented by formula (1) and a second photosensitive compound represented by formulae (2a) or (2b); (ii) a resin; and (iii) a solvent. The invention enables the formation of patterns with an exceptional profile due to a high degree of sensitivity and resolution of the photoresist composition.

Abstract: A photosensitive polymer having a main chain consisting of only norbornene-type alicyclic units, a resist composition containing the photosensitive polymer and a preparation method thereof, wherein the photosensitive polymer is represented by the following formula: wherein R1 is an acid-labile tertiary alkyl group, R2 is &ggr;-butyrolactone-2-yl, &ggr;-butyrolactone-3-yl, pantolactone-2-yl, mevalonic lactone, 3-tetrahydrofuranyl, 2,3-propylenecarbonate-1-yl or 3-methyl-&ggr;-butyrolactone-3-yl, R3 is a hydrogen atom, methyl, ethyl or C3 to C20 alicyclic hydrocarbon, and p/(p+q+r) is 0.1˜0.8, q/(p+q+r) is 0.2˜0.8, and r/(p+q+r) is 0.0˜0.4. To prepare the photosensitive polymer, at least two different norbornene-type compounds having an ester group as a substituent are reacted in the presence of an initiator at a temperature of about 120 to about 150 ° C. without a reaction catalyst.

Abstract: A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer on a semiconductor substrate forming a photoresist pattern, using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer, using the same photoresist pattern as an etching mask and anisotropically etching remainder second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate, removing the photoresist pattern, using radio frequency (RF) etching to remove a reverse slope of the via hole and forming a metal plug in the via hole.

Abstract: A protective film separator comprising an adsorption means and a peeling means for removing the protective film in a semiconductor wafer backside grinding process. The adsorption means uses a vacuum to separate a part of a protective film adhered to an electrical circuit patterned side of a wafer from the patterned side of the wafer. The peeling means presses each side of the part of the protective film separated from the wafer by the adsorption means, and separates unpeeled parts thereof from the patterned side of the wafer. The protective film separator of the present invention reduces costs and expenses for raw materials by eliminating the need for extra removing tape or heat-activated adhesive tape. The present invention may also improve semiconductor yields by reducing the external force applied to a wafer during removal of the protective film, thereby allowing better protection from impurities.

Abstract: A semiconductor contact structure for a merged dynamic random access memory and a logic circuit (MDL) and a method of manufacturing the contact structure to: (i) a cell contact pad; (ii) at least one active region; and (iii) at least one gate electrode simulaneously, whereby an electric short between the gate electrodes and the cell contact pad is avoided, even in the event a lithographic misalignment occurs and whereby it is possible to obtain an overlap margin in the cell region, even with an improved metal contact to the gate electrode in the peripheral circuit region of the semiconductor device.

Abstract: A semiconductor device for performing a static random access memory operation includes a plurality of refresh type memory cells provided at intersections of a plurality of word lines and a plurality of bit lines, a high voltage generator providing a voltage higher than a power source voltage to a stand-by high voltage output node in response to a driving control signal activated in a memory cell access operation period, an internal circuit related to word line driving for selecting a word line among the plurality of word lines using the high voltage in response to command information and address information, and a driving control signal generator generating the driving control signal in response to the command information to operate the high voltage generator prior to initial charge consumption in the stand-by high voltage output node during the memory cell access operation period.

Abstract: A bubble-jet type inkjet printhead, a manufacturing method thereof and a method of ejecting ink, wherein, in the printhead, a manifold supplying ink, a hemispherical ink chamber, and an ink channel for connecting the manifold with the ink chamber are integrally formed on the substrate. A nozzle plate on the substrate having a nozzle, and a heater formed in an annular shape and centered around the nozzle are integrated without a complex process such as bonding. Thus, this simplifies the manufacturing process and facilitates high volume production. Furthermore, according to the ink ejection method, a doughnut-shaped bubble is formed to eject ink, thereby preventing a back flow of ink as well as formation of satellite droplets that may degrade image resolution.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays. Each of the memory cell arrys includes a plurality of memory blocks. A row decoder is located adjacent to the memory cell array. Capacitance of the memory block becomes smaller as the memory block location becomes farther from the row decoder.

Abstract: An ultra-thin semiconductor package device comprises a heat-resistant film-type adhesive support tape which connects a semiconductor chip to a plurality of individual lead frames, wherein each lead frame is connected to an associated one of a plurality of electrode pads of the semiconductor chip by a plurality of bonding wires. An encapsulating molding material provides environmental protection for the completed package. Within the encapsulating molding, the semiconductor chip is mounted on a same underside of the support tape as the plurality of lead frames, such that the bottom of the semiconductor chip is aligned with the bottom of an encapsulating molding, and the height of a loop in each bonding wire is minimized.

Abstract: A method of forming fine patterns of semiconductor devices comprises patterning one material layer using at least two sub-photomasks. The material layer is formed on a semiconductor substrate, and the material layer is patterned at least twice using each of the sub-photomasks. The shapes and sizes of the patterns on one sub-photomask are different to those of the other sub-photomask, and the patterns of one sub-photomask may partially overlap those of the other sub-photomask. The profiles of all patterns formed on the one material layer can thereby be optimized.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: A styrene random copolymer includes at least one unit of styrene derivative and at least one unit of macromonomer. The at least one unit of styrene derivative is polymerized from a styrene derivative monomer of formula (1). The at least one unit of macromonomer is polymerized from a macromonomer of formula (2). In formulae (1) and (2), R1 is selected from the group consisting of hydrogen, halogen, and alkyl groups with 1˜20 carbon atoms, R2 is at least one selected from the group consisting of saturated hydrocarbons with 1˜20 carbon atoms, aromatic groups, and cycloalkyl groups with the proviso that R2 is not —CO— or —CH2—C6H4—, R3 is a saturated hydrocarbon group with 1˜10 carbon atoms, X is at least one ion polymerizable monomer unit. The amount of the macromonomer is 0.

Abstract: A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: An inkjet printhead includes a nozzle plate having a nozzle, a substrate having an ink feed hole, and an intermediate layer interposed between the nozzle plate and the substrate, wherein the intermediate layer includes an ink chamber connected to the ink feed hole and the nozzle and a heating element surrounding the ink chamber. In the present invention, the nozzle, the ink chamber, and the ink feed hole are formed in a straight channel, thereby providing a high density printhead.

Abstract: A semiconductor device having improved metal line structure has a first dielectric layer formed on a semiconductor substrate, a metal film pattern formed on the first dielectric layer, an interface protection layer on the metal film pattern, and a second dielectric layer on the interface protection layer, wherein the second dielectric layer contains a reactive material, e.g., fluorine, which is prevented by the interface protection layer from diffusing to the metal film pattern and reacting with the metal in the metal film pattern to form a damage film, e.g., metal fluoride, which is a highly resistive material that, if formed on the semiconductor device, would reduce the reliability of the metal film pattern and thus reduce the reliability of the semiconductor device as a whole.

Abstract: A magnetic random access memory with write and read circuits using magnetic tunnel junction (MTJ) devices wherein MTJs are arranged at cross points of word lines and read bit lines to form memory cells. After write bit lines and read bit lines are arranged parallel to each other, current bypass paths are formed allowing current to bypass the side and bottom of the MTJ. Thus, an electric field having intensity enough to change the magnetization direction of the MTJ, is applied only to each selected cell. In a write operation, the magnetization direction of a free layer in the MTJ is formed to be parallel or antiparallel to the magnetization direction of a pinned ferromagnetic layer by the current passing through the word line and the current bypass path.