Abstract: A method for etching a metal layer on a scale of nano meters, includes preparing a substrate on which a metal layer is formed, positioning a micro tip over the metal layer, generating an electron beam from the micro tip by applying a predetermined voltage between the metal layer and the micro tip, and etching the surface of the metal layer into a predetermined pattern with the electron beam. Accordingly, it is possible to form an etched pattern by applying a negative bias to a micro tip without applying a strong mechanical force to the micro tip, and heating/melting the metal layer with the use of an electron beam emitted from the micro tip which is negative-biased.

Abstract: A monolithic nozzle assembly formed with a mono-crystalline silicon substrate includes a damper for temporarily storing an incoming fluid, and a nozzle having a pyramidal portion and an outlet portion, the pyramidal portion for guiding the flow of the fluid from the damper toward the outlet portion and for increasing the pressure of the fluid, and the outlet portion through which the fluid is discharged, wherein the damper, and the pyramidal and outlet portions of the nozzle are aligned with each other and formed in the single mono-crystalline silicon substrate by continuous processes. The monolithic nozzle assembly can be formed with a single (100) mono-crystalline silicon wafer. Compared with a complicated nozzle assembly formed using a great number of silicon wafers and plates, the configuration of the monolithic nozzle assembly is simple, and can be manufactured on a mass production scale by semiconductor manufacturing processes.

Abstract: The present invention relates to a capacitor of a semiconductor memory cell and a method of manufacturing the same wherein a capacitor includes a first insulation layer having a buried contact hole, formed on a semiconductor substrate, and a buried contact plug filling a portion of the buried contact hole. A diffusion barrier spacer is formed on an inner surface of the buried contact hole above the buried contact plug. A second insulation layer is formed, having a through hole larger than the buried contact hole, for exposing the diffusion barrier spacer and a top surface of the contact plug. A barrier layer is formed on the through hole and a lower electrode is formed on the barrier layer. A dielectric layer is formed on the lower electrode and an upper surface of the second insulation layer and an upper electrode is formed on the dielectric layer.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: An air-sampling carrier for sampling air from a clean room of a semiconductor processing facility, an apparatus and a method for analyzing the air, wherein the air-sampling carrier includes a container having an inner space, a door mounted at a front wall of the container, a discharging pipe for discharging the air sample out of the container, and at least one inlet tube for introducing purge gas into the inner space of the container from outside the container. The discharging pipe and inlet tube are respectively formed on an outer surface of the container and connected to an inner space of the container. The air in the unit process tools is effectively sampled using an unmanned carrying apparatus and the pollution level of the air sample is simply and easily measured.

Abstract: A method of forming a gate electrode, capable of minimizing a resistance difference between the gate electrodes and a method of forming a non-volatile memory device using the same, wherein an oxide film pattern, a polysilicon layer pattern and a hard mask pattern are stacked on a semiconductor substrate to form a gate structure; a gate spacer including an oxide-based insulating material is formed on a sidewall of the gate structure; the hard mask pattern stacked on the gate structure is removed to expose the polysilicon layer pattern; the polysilicon layer pattern and the top portion of the gate spacer are planarized; a stopping layer and an insulating interlayer are then formed and planarized by CMP. Thus, the thickness of the films for forming the gate electrode and, consequently the gate electrode resistance of a semiconductor device, are uniform across the wafer.

Abstract: A high-density ink-jet printhead, in which a plurality of nozzles, through which ink is ejected, are arrayed on an ink supply manifold in a plurality of rows is provided, wherein the ink-jet printhead includes a substrate; hemispherical ink chambers at a surface of the substrate; a manifold for supplying ink to the ink chambers; ink channels to be in flow communication with the ink chambers and the manifold; a nozzle plate monolithically formed with the substrate; nozzles formed on the nozzle plate, each formed to correspond to a center of each of the ink chambers; heaters formed on the nozzle plate, each having a ring shape and encircling a corresponding nozzle; and electrodes, positioned on the nozzle plate and electrically connected to the heaters, for applying current to the heaters, wherein the nozzles are arrayed on the manifold in at least in three rows, and preferably in five rows.

Abstract: A method for forming a contact hole in a semiconductor device includes the steps of forming a polymer layer on an upper portion and a side wall of photo resist mask, while etching an oxide layer under the photoresist mask to form a contact hole that uses an etchant gas comprising CH2F2 gas; and etching the oxide layer while stopping the supply of CH2F2 gas to the etching process.

Abstract: A digital subscriber line receiving apparatus having resilience to HAM radio interference noise and a method therefore includes an automatic gain controller for amplifying a received signal level to a signal level having a predetermined magnitude, a timing recoverer for recovering timing from a signal output from the automatic gain controller, an equalizer for removing interference noise from a signal received from the timing recoverer, a slicer for detecting a digital value from a signal received from the equalizer, an initialization controller for resetting the receiving apparatus and initializing the automatic gain controller, the timing recoverer, and the equalizer when the signal to noise ratio of the output signal of the equalizer is smaller than a reference signal to noise ratio, and an update controller for preventing automatic gain controller and equalizer from being initialized by the initialization controller when HAM radio interference noise is detected in the received signal.

Abstract: A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.

Abstract: A polishing pad conditioning apparatus in a chemical mechanical polishing apparatus, wherein the conditioning apparatus includes a conditioning plate which maintains a predetermined relative velocity with respect to the polishing pad, extends from a center region near a rotation center of the polishing pad to a peripheral region near an edge of the polishing pad, and has a polishing portion with polishing particles embedded into its bottom surface, a force generating portion for applying a force to the conditioning plate so that the conditioning plate presses against the polishing pad with pressure that varies according to position on the polishing pad, and conditions the polishing pad by relative linear velocity and pressure with respect to the polishing pad, and a supporting portion for supporting the force generating portion. Therefore, fast and uniform conditioning of a polishing pad can be achieved.

Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

Abstract: A semiconductor integrated circuit wafer tester includes a supporting plate on which a semiconductor wafer may be positioned and a tester head having a circular top plate installed a predetermined distance away from the supporting plate, wherein a probe card in the tester head that includes a circular printed circuit board having a diameter of at least 400 mm (15.75 inches) that is connected to the top plate and having a plurality of probe units formed on the printed circuit board allows electrical parameters of multiple chips formed on the semiconductor wafer to be measured simultaneously.

Abstract: A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Abstract: A field emission array adopting carbon nanotubes as an electron emitter source, wherein the array includes a rear substrate assembly including cathodes formed as stripes over a rear substrate and carbon nanotubes; a front substrate assembly including anodes formed as stripes over a front substrate with phosphors being deposited on the anodes, a plurality of openings separated by a distance corresponding to the distance between the anodes in a nonconductive plate, and gates formed as stripes perpendicular to the stripes of anodes on the nonconductive plate with a plurality of emitter openings corresponding to the plurality of openings. The nonconductive plate is supported and separated from the front substrate using spacers. The rear substrate assembly is combined with the front substrate assembly such that the carbon nanotubes on the cathodes project through the emitter openings.

Abstract: A high-energy ion implanter for fabricating a semiconductor device includes a low-energy accelerator for converting a polarity of ions flowed in from an ion source; a stripper for converting the ions accelerated from the low-energy accelerator to positive ions in vacuum conditions; a high-energy accelerator for accelerating, in high-energy, the positive ions that are converted in the stripper; a turbo pump for providing vacuum conditions in the stripper; a current sensor for detecting currents to check for abnormal operating conditions of the turbo pump; and a central processing unit (CPU) that interrupts a circuit breaker to suspend the ion implanting process in response to the level of current detected in the current sensor. The high-energy ion implanter of the present invention is capable of preventing an unsuccessful ion implanting process by suspending operation thereof when abnormal operating conditions are detected.

Abstract: A method of fabricating a DRAM semiconductor device including forming gate stacks in which a gate pattern and a gate sacrificial mask are sequentially deposited on a semiconductor substrate, forming an etch stopper on the semiconductor substrate, forming a lightly doped impurity region between the gate stacks, forming a gate spacer along sidewalls of the gate stacks, forming a heavily doped impurity region to contact the lightly doped impurity region and to be aligned with the gate spacer, removing the gate spacer, forming an interlevel dielectric layer to fill a gap between the gate stacks, forming a groove on a gate conductive layer by etching an exposed top surface of the etch stopper and the gate sacrificial mask, forming a contact mask pattern for filling the groove, forming a contact hole to be self-aligned with respect to the contact mask pattern, and forming a contact pad in the contact hole.

Abstract: A panel defining a front exterior of a cathode ray tube has an inner surface overlaid with a phosphor screen, and an outer surface overlaid with a tinted coating layer, wherein the tinted coating layer varies light transmission at the center and the periphery of the panel by being dark at the center and gradating brighter toward the periphery thereby preventing a difference in brightness of the panel between the center and the periphery thereof due to incremental growth in the volume of a black matrix and in the thickness of the panel toward the periphery.

Abstract: A solder structure comprising a radially-curved exterior surface enclosing a predetermined-sized cavity used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar properties. By assembling the two planar elements in a tiered arrangement, one planar element having an annular conductive pad and the other planar element having either a corresponding annular or circular conductive pad, separated by a spherical solder compound comprised of solder and a fluxing agent, a hollow solder structure can be created during a melting and subsequent cooling of the solder compound. The plasticity/resiliency characteristics of the resulting hollow solder structure absorbs lateral movement of the two planar elements relative to each other without degradation of the solder joint.

Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.