Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: A sonic water level measuring method and system for mounting a wave-guide tube for measuring a water level in a reservoir, a river, etc. generating sonic pulses at the upper of the wave-guide tube, measuring transit times that it takes for the sonic pulses to transit from an original point to a water surface through air medium and transit back to the original point after being reflected on the water surface and multiplying the transit times by a sound velocity to compute a water level is configured to measure the sound velocity using the times that it takes for the sonic pulse to transit in two intervals in order to exactly measure the sound velocity that is changed according to the changing of an air temperature, pressure and component in the wave-guide tube and then measure the water level considering an arithmetical average value of the sound velocities measured as a sound velocity in the wave-guide tube.

Abstract: A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: Apparatus and method for measuring concentration of a component of target material including a pumping light source for emitting light; a first wavelength conversion unit for converting and outputting the light; a first beam splitting unit for splitting the converted light and directing a first light beam at the target material; a reference light generator for converting a second light beam to be parallel, dividing the parallel light beam by wavelengths, and outputting the result as reference light; a first collimating unit for converting light transmitted through the target material to be parallel and outputting the parallel light; a light intensity measuring unit for measuring the intensity of light from the first collimating unit and the reference light, by wavelengths, using the reference light; and a concentration measuring unit for measuring the concentration of the component based on the intensities measured by the light intensity measuring unit by wavelengths.

Abstract: In a method of manufacturing a non-volatile memory or other semiconductor device, a control gate made of conductive material is formed in a more uniform fashion. The method includes forming a silicon layer on a buffer oxide layer on a semiconductor substrate. After forming the buffer oxide layer, a stopping layer is formed. The control gate of conductive material, such as a floating gate in an EEPROM memory device, is provided by patterning the silicon layer, gate oxide layer, and the substrate, and then, a trench is formed in the upper portion of the substrate. Uniformity is achieved by oxidizing the sidewalls of the trench to create bird's beaks at both upper and lower portions of the control gate material. Then, a field oxide layer that fills up the trench is formed.

Abstract: The present invention relates to an apparatus for cutting a wafer, wherein the wafer cutting process is performed along a back side of a wafer, a semiconductor chip being formed on the front side thereof, by cutting the wafer along the back side of the wafer by directly recognizing the semiconductor chip shape formed on the front side of the wafer thereby minimizing cutting defects due to sawing blade misalignment. The present invention includes a hole formed in the center portion of a chuck table on which the wafer, which is facing down, is attached and a camera installed under the hole of the chuck table. After the wafer is properly aligned by the camera recognizing the semiconductor chip shape formed on the front side of the wafer, a wafer cutting process is performed by a sawing blade.

Abstract: A process for preparing an 1,3-alkanediol from a 3-hydroxyester includes hydrogenating a 3-hydroxyester in an alcohol-containing solvent in the presence of a hydrogenation catalyst prepared by adding an alkaline precipitator to an aqueous solution containing a copper salt to form particles, and then aging the particles following addition of colloidal silica thereto. Novel hydrogenation catalysts so prepared are also disclosed.

Abstract: A process for preparing a 1,3-alkandiol from a 3-hydroxyester, comprises preparing a catalyst by adding an alkaline precipitator to an aqueous copper salt solution to form copper hydroxide particles, and aging the particles following the addition of a colloidal silica thereto; activating the catalyst by reduction with a H2 gas or a H2-containing gas and applying a pressure of about 5 psig to about 2000 psig at a temperature of about 100° C. to about 250° C. in the presence of an activation solvent; and hydrogenating a 3-hydroxyester in a liquid phase slurry with a H2 gas or a H2-containing gas and applying a pressure of about 50 psig to about 3000 psig at a temperature of about 100° C. to about 250° C. in the presence of the activated catalyst and a reaction solvent, whereby a 1,3-alkanediol can be selectively prepared from a 3-hydroxyester with a high yield.

Abstract: A method of manufacturing a carbon nanotube field emitter for field emission displays by electrophoresis is disclosed. The method of manufacturing involves: first, loading an electrode plate and the field emitter substrate, which are spaced apart from one another, into an electrophoresis bath containing a carbon nanotube suspension for the electrophoresis; second, applying a predetermined bias voltage from a power supply between the electrode plate and the cathodes of the field emitter substrate to deposit, at room temperature, carbon nanotube particles on the surface of the electrodes exposed through the holes of the dielectric film; and third, drawing the field emitter substrate, on which the carbon nanotube particles have been deposited, out of the electrophoresis bath, and heating the field emitter substrate with carbon nanotube tips at a predetermined temperature. An efficient low-temperature process, incorporating low cost carbon nanotube particles, provides for a lower manufacturing cost.

Abstract: A photosensitive polymer having a phenyl ring and a lactone group, and a resist composition, wherein the resist composition contains a photosensitive polymer including a monomer unit having at least one group selected from the groups indicated by the following formulas, and a photoacid generator (PAG).

Abstract: A copper-plating electrolyte includes an aqueous copper salt solution, a water-soluble &bgr;-naphtholethoxylate compound having the formula wherein n is an integer from 10 to 24, one selected from the group consisting of a disulfide having the formula XO3S(CH2)3SS(CH2)3SOX3 and a water-soluble mercaptopropanesulfonic acid or salt thereof having the formula HS(CH2)3SO3X, where X is sodium, potassium, or hydrogen, a water-soluble polyethylene glycol having a molecular weight ranging from about 4,600 to about 10,000, and a water-soluble polyvinylpyrrolidone having a molecular weight ranging from about 10,000 to about 1,300,000.

Abstract: A method of forming self-aligned contacts in a semiconductor device wherein a silicon nitride layer and a polysilicon layer are formed on a gate electrode layer. The polysilicon layer, the silicon nitride layer, and the gate electrode layer are etched to form gate electrode configurations. Sidewall spacers are formed on both sidewalls of the gate electrode configurations. An oxide layer is then deposited on the resulting structure. Selected portions of the oxide layer are etched to form self-aligned contacts that expose the semiconductor substrate. Because the polysilicon has an excellent etch selectivity with respect to the oxide layer, the gate electrode layer can be sufficiently protected during the etching of the oxide layer resulting in a good shoulder margin at the exposed upper edges of the silicon nitride gate mask layer.

Abstract: A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

Abstract: A method of reducing PFC emissions during a semiconductor manufacturing process that includes a set of sub-processes each of which produces at least one PFC includes the steps of exhausting PFC's produced by each sub-process to a common line to form a combined exhaust stream, treating the combined exhaust stream from each sub-process using a separate PFC abatement system, combining the treated exhaust streams to form a combined treated stream, and wet scrubbing the combined treated stream.

Abstract: A polyamic ester prepared by partially substituting hydrogen atoms of carboxylic groups of a polyamic acid with acid labile groups, the polyamic ester comprising one or more repeating units represented by Formula 1, and each of at least one terminal of the polyamic ester molecule terminates with the same or different reactive end-capping monomer: wherein in Formula 1, R1 and R2 are independently a hydrogen atom, or an acid labile group; X is a tetravalent, an aromatic or an aliphatic organic group; Y is a divalent, an aromatic or an aliphatic organic group; and m is an integer equal to or greater than 1.

Abstract: A bubble-jet type ink-jet printhead, includes a substrate, a nozzle plate, a wall, and a heater, wherein the heater is interposed between the substrate and the nozzle plate to divide an ink chamber into a main ink chamber and a secondary ink chamber, wherein a main bubble and a secondary bubble are generated. The printhead may further include an ink channel for introducing ink into the secondary ink chamber for supplying the ink to the main ink chamber. The printhead according to the present invention consumes less energy, prevents a backflow of ink, and operates at increased speed.

Abstract: A wafer drying apparatus of increased efficiency in which isopropyl alcohol (IPA) supplied to a hood is activated by heat, thereby increasing its diffusion efficiency and enabling it to vaporize pure water on a wafer quickly, includes a washing tank for storing pure water, a hood positioned at an upper portion of the washing tank, an injection nozzle for ejecting IPA positioned in the hood, a storage tank for storing the IPA, a bubble maker in the storage tank to create IPA vapor, a nitrogen supplier for storing a carrier gas for transferring the IPA vapor in the storage tank to the hood, and a heater provided near the injection nozzle to heat the IPA vapor that is ejected through the injection nozzle to a predetermined temperature, thereby uniformly diffusing the IPA vapor.

Abstract: A semiconductor device and a method for manufacturing the same, wherein a gate electrode structure is formed on a surface of a semiconductor substrate. Next, a gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on the semiconductor substrate. Then, the surface of the semiconductor substrate is cleaned to remove any residue and the GPOX layer remaining on the semiconductor substrate. Next, an etch stopper is formed on the surface of the gate electrode structure and on the semiconductor substrate. Last, a high-density plasma (HDP) oxide layer is deposited on the etch stopper. The semiconductor device and method for manufacturing the same are capable of preventing bubble defects.

Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.