Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.

Abstract: A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.

Abstract: A method for manufacturing a ferroelectric thin film using a sol-gel process comprising the steps of dissolving a Pb precursor using a solvent to prepare a Pb solution and stabilizing a Zr precursor and a Ti precursor to prepare a Zr solution and a Ti solution, respectively, mixing the Zr solution and Ti solution, stirring the Ti—Zr mixed solution with the Pb solution and hydrolyzing to prepare a ferroelectric solution, and forming a ferroelectric thin film on a substrate using the ferroelectric solution.

Abstract: A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

Abstract: An ink-jet printhead having a hemispherical ink chamber and a method for manufacturing the same, wherein the ink-jet printhead includes a substrate, in which a manifold for supplying ink, an ink chamber having a substantially hemispherical shape, and an ink channel for supplying ink from the manifold to the ink chamber are integrally formed; a nozzle plate having a multi-layered structure, in which a first insulating layer, a thermally conductive layer formed of a thermally conductive material, and a second insulating layer are sequentially stacked, and having a nozzle, formed at a location corresponding to the center of the ink chamber; a nozzle guide having a multi-layered structure and extending from the edge of the nozzle to the inside of the ink chamber; a heater formed on the nozzle plate to surround the nozzle, and an electrode formed on the nozzle plate to be electrically connected to the heater.

Abstract: The present invention discloses a layout in a semiconductor device having conductive layers electrically connected to conductive regions via contact holes beneath the conductive layers. Each of the conductive layers has a layout with different widths at opposite longitudinal ends thereof, respectively, thereby being capable of achieving an improvement in the alignment margin between the conductive layer and the contact hole within a given memory cell area. Where the layout is applied to capacitors, it is possible to avoid the formation of inferior storage electrodes over regions where contact holes are formed.

Abstract: A method for fabricating a cylindrical capacitor that exceeds photolithographic resolution. The capacitor is formed by partially etching the storage node opening, thereby reducing the distance between adjacent openings defined by the photolithographic process. The openings defined by the photolithographic process is enlarged by wet etching the sidewalls of the openings by at least the same thickness as that of a subsequently formed conductive layer for storage node formation. Contact plugs that are electrically connected to the bottom of the cylindrical storage nodes protrude from the top surface of an insulating layer in order to increase process margins and decrease contact resistance.

Abstract: In a voltage generator having a voltage level detector, an oscillator, and a voltage pump, the voltage level detector comprises an amplifier, which, in combination with a first and a second linear current source, provides accurate control of an output voltage of the voltage generator. When a sensed voltage deviates around a reference voltage, a differential detection by the amplifier of this deviation causes the oscillator and the voltage pump to provide a corresponding increase or decrease in the magnitude of an output voltage in order to compensate for the deviation. Use of the amplifier and a predetermined reference voltage allows for an accurate threshold detection level for low-voltage, high-speed operation of the voltage generator. The present invention can be used in both positive and negative voltage generators.

Abstract: A semiconductor device having a self-aligned contact and a method for forming the same, including a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; a self-aligned contact exposing a portion of the self-aligned contact region; a first insulating layer formed on the semiconductor substrate that exposes the self-aligned contact; conductive patterns formed on the first insulating layer and spaced apart from each other; spacers formed on sidewalls of each of the conductive patterns; a second insulating layer formed over the first insulating layer that exposes the self-aligned contact; a third insulating layer formed between the second insulating layer and the spacer; a fourth insulating layer formed over the non-self-aligned contact region and on sidewalls of the spacers over the self-aligned contact region; and a fifth insulating layer formed on a portion of the fourth insulating layer over the non-self-aligned contact region.

Abstract: An apparatus for attaching an object semi-automatically onto a dummy wafer comprising a stage having a loading surface on which the dummy wafer rests, a pressing device for attaching the object gradually onto the dummy wafer placed on the loading surface, and a supporting device for placing the object in a position spaced apart from the loading surface.

Abstract: A photo-alignment material useful in liquid crystal alignment films comprises a maleimide-based repeating unit and at least one additional repeating unit, or a maleimide-based repeating unit and at least two additional repeating units. The photo-alignment materials have freely-controllable pretilt angles, and they provide a display quality equivalent or superior to alignment materials made using the conventional rubbing process.

Abstract: A multi-layer film for a thin film structure, a capacitor using the multi-layer film and methods for fabricating the multi-layer film and the capacitor, the multi-layer film including a composition transition layer between a lower material layer and an upper material layer respectively formed of different elements whose interaction parameters are different from each other, the composition transition layer containing both elements of the lower and upper material layers, the concentration of the composition transition layer gradually varying from the portion of the composition transition layer contacting with the lower material layer to the portion of the composition transition layer contacting with the upper material layer such that the concentration of the element of the upper material layer is relatively large in its portion adjacent to the upper material layer, each of the lower and upper material layers being formed of an oxide or nitride material of aluminum, silicon, zirconium, cerium, titanium, yttrium,

Abstract: A method and an apparatus for pyroelectric lithography using a patterned emitter is provided. In the apparatus for pyroelectric lithography, a pyroelectric emitter or a ferroelectric emitter is patterned using a mask and it is then heated. Upon heating, electrons are not emitted from that part of the emitter covered by the mask, but are emitted from the exposed part of the emitter not covered by the mask so that the shape of the emitter pattern is projected onto the substrate. To prevent dispersion of emitted electron beams, which are desired to be parallel, the electron beams are controlled using a magnet or a projection system, thereby achieving exact a one-to-one projection or a x-to-one projection of the desired pattern etched on the substrate.

Abstract: A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH2NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A non-volatile semiconductor device and a method of making such a device having a memory cell formation part and a peripheral circuit part having high and low-voltage transistor formation parts, wherein the device includes an anti-punch through region surrounding a drain region in the memory cell formation part, and surrounding drain and source regions of the low-voltage transistor formation part.

Abstract: A method of preparing an object with a radially-varying property is disclosed which includes the steps of providing a preform reactor including an outer container having a bottom, an inner container installed in the outer container, the inner container having a bottom, a rotating rod installed at a position in the outer container, and a sealing member for sealing the outer and inner containers at the bottoms thereof; filling the inner container with an inner material and a space between the inner container and the outer container with an outer material wherein the outer material has a different property from the inner material; removing the inner container; and rotating the rotating rod for laminar mixing of the inner and outer materials. An apparatus for carrying out the inventive method, and objects formed in accordance with the inventive method, are also disclosed.

Abstract: A bubble-jet type ink-jet printhead and manufacturing method thereof including a substrate integrally having an ink supply manifold, an ink chamber, and an ink channel; a nozzle plate having a nozzle on the substrate; a heater centered around the nozzle and an electrode for applying current to the heater on the nozzle plate; and an adiabatic layer on the heater for preventing heat generated by the heater from being conducted upward from the heater. Alternatively, a bubble-jet type ink-jet printhead may be formed on a silicon-on-insulator (SOI) wafer having a first substrate, an oxide layer, and a second substrate stacked thereon and include an adiabatic barrier on the second substrate. In the bubble-jet type ink-jet printhead and manufacturing method thereof, the adiabatic layer or the adiabatic barrier is provided to transmit most of the heat generated by the heater to ink under the heater, thereby increasing energy efficiency.

Abstract: A ferroelectric capacitor with a multilayer ferroelectric film to prevent degradation of its ferromagnetic characteristics, wherein the ferroelectric film is made of a lower layer of PZT or PLZT formed on a lower electrode and an upper, titanium rich, layer of PZT, PLZT, or PbTiO3, an upper electrode formed on the upper layer of the ferroelectric film and a protective layer formed to cover the ferroelectric capacitor.

Abstract: A semiconductor memory device and a method of manufacturing same, wherein landing pads are formed to contact source/drain regions of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. An interlayer insulation layer is deposited on the resultant structure, and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.