Abstract: An apparatus for measuring the focus of a light exposure system for selectively exposing a photosensitive plate to light rays in a process of fabricating a semiconductor device, wherein there is provided a focus measuring part having opaque region, transparent region, and a transparent electrode arranged in the transparent region, a conducting stage supporting the photosensitive plate; and a capacitance detector for measuring the capacitance between the transparent electrode and the conducting stage.

Abstract: The photoacid generator according to the present invention is represented by the general formula (1): wherein R1 and R2 are respectively H, OH or alkyl or alkoxy group of C1-5 and are the same or different, n is an integer from 1 to 3, and Ar1 is a naphthalene unit. The photosensitive resin used in a composition of the invention is represented by the general formula (2): wherein X is a tetravalent aromatic or aliphatic organic radical, Y is a bivalent aromatic or aliphatic organic radical, and R3 and R4 independently are H or a monovalent aliphatic organic protecting group removable by acid.

Abstract: A process for preparing an 1,3-alkanediol through carbonylation of an epoxide derivative includes the steps of (a) reacting an epoxide derivative with alcohol and carbon monoxide in a solvent at a temperature from about 30 to about 150° C. and at a pressure from about 50 to about 3000 psig in the presence of a catalyst system including an effective amount of a cobalt catalyst and an effective amount of a promoter to afford a reaction mixture including a 3-hydroxyester or derivative thereof in an amount of from 2 to about 95% by weight, (b) separating the reaction product and solvent from the catalyst and promoter, (c) reacting said reaction product and solvent with hydrogen at a temperature from about 30 to about 350° C. and at a pressure from about 50 to about 5000 psig in the presence of a catalyst system for hydrogenation to prepare a hydrogenation product mixture including a 1,3-alkanediol, and (d) recovering the 1,3-alkanediol from the hydrogenation product mixture.

Abstract: A bubble-jet type ink-jet printhead, and a manufacturing method thereof are provided, wherein, the printhead includes a substrate integrally having an ink supply manifold, an ink chamber, and an ink channel, a nozzle plate having a nozzle, a heater consisting of resistive heating elements, and an electrode for applying current to the heater. In particular, the ink chamber is formed in a substantially hemispherical shape on a surface of the substrate, a manifold is formed from its bottom side toward the ink chamber, and the ink channel linking the manifold and the ink chamber is formed at the bottom of the ink chamber. Thus, this simplifies the manufacturing process and facilitates high integration and high volume production. Furthermore, a doughnut-shaped bubble is formed to eject ink in the printhead, thereby preventing a back flow of ink as well as formation of satellite droplets that may degrade image resolution.

Abstract: A method of removing metal-containing polymeric material and ion implanted or plasma damaged photoresist from a surface using a plasma jet system, by generating radicals having high energy and high density from atmospheric plasma by introducing a reactant gas to the plasma, and placing the surface at a distance from the plasma, whereby ionic reaction on the surface is minimized while the removing action of the radicals on the surface is maintained.

Abstract: A self-aligned contact structure in a semiconductor device and methods of forming the same are provided, wherein the self-aligned contact structure in the semiconductor device comprises a semiconductor substrate having active regions; an interlayer insulating layer covering the semiconductor substrate excluding at least a portion of each active region; at least two parallel interconnections on the interlayer insulating layer, at least one active region being relatively disposed between the at least two parallel interconnections, each interconnection having sidewalls, a bottom and a width (x); a mask pattern having a top portion of width (z) and a bottom portion of width (y) formed on each interconnection; and a conductive layer pattern penetrating at least a portion of the interlayer insulating layer between the mask pattern and being electrically connected to at least one active region, wherein x≦y≦z and x<z.

Abstract: A water-soluble polymeric adhesion promoter is represented by the following formula (I): wherein R is a hydrogen atom, a hydroxyl group or a lower alkyl group having 1 to 4 carbon atoms, and m and k are numbers selected such that m/k is in the range from about 1/0.001 to about 1/0.1, and such that that the polymer (I) has a weight average molecular weight of about 3,000 to about 600,000.

Abstract: A reference voltage generating circuit of the present invention includes a start-up circuit connected between a power supply voltage and a ground voltage for generating a start-up voltage, a bias current generating circuit connected between the power supply voltage and the ground voltage for generating a bias current in response to the start-up voltage, the bias current increasing in response to an increase in temperature, a current generator connected between the power supply voltage and a reference voltage generating terminal for generating a mirrored current of the bias current, and a load connected between the reference voltage generating terminal and the ground voltage for generating a reference voltage that increases in response to any increase in temperature regardless of variations in the level of the power supply voltage. Accordingly, the level of reference voltage generated increases in response to increases in temperature regardless of variations in the level of the power supply voltage.

Abstract: A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

Abstract: A semiconductor integrated circuit device of an embodiment of the present invention includes a voltage converting transistor, connected between a pad and an internal circuit, for converting an input voltage applied to the pad into a voltage that is lower than an operating voltage of the internal circuit, a first pull-up transistor connected between the operating voltage and the pad, a second pull-up transistor connected between the operating voltage and a junction node connecting the voltage converting transistor with the internal circuit, and a control circuit for controlling the first and second pull-up transistors so that the first and second pull-up transistors operate complementary to each other, according to a voltage on the pad when the pad is in a floating condition.

Abstract: A digital phase interpolator including a plurality of delay stages to control delay time of an output signal from first and second input signals having different phase delays. The plurality of delay stages are connected serially, have a same internal structure, determine corresponding axes for interpolation in each stage, and each includes a first inverting section for inverting first and second signal inputs from the previous stage, a phase blender for blending outputs of the first inverting section, a second inverting section for inverting outputs of the first inverting section, and a multiplexer for generating input signals for the next stage in response to a selection signal for determining phase delay time of the output signal of the phase interpolator. Total area and current may be reduced by the present invention because the number of inverters comprising each stage is equal.

Abstract: A tension measurement apparatus for a pogo pin having a height adjusting device for adjusting a height to be measured vertically, on which a device for measuring a tension of the pogo pin is mounted to be vertically movable according to the operation of the height adjusting device. The measurement apparatus preferably includes a vertical moving supporter mounted on the height adjusting device, a fixing member disposed to be coupled with or separated from the vertical moving supporter, a moving rail rotatably connected to the fixing member, a coupler mounted on the moving rail to be movable within the range of a given distance, connected to the tension measurement device. The tension measurement apparatus of the present invention can measure the tension of pogo pins under uniform conditions, while the pogo pins remain in a pogo module, thereby preventing inspection errors due to the pogo pins.

Abstract: State change transition times of a semiconductor memory device is reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharging circuits and non-shared I/O lines which have only a single precharging circuit, effective contact resistance of the non-shared I/O lines are reduced by eliminating unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.

Abstract: A non-volatile memory device and a fabrication method thereof, wherein the non-volatile memory device includes first and second memory cells in a region of a semiconductor substrate where a word line crosses a bit line. Thus, one word line can control the operation of two memory cells, and the device requires less area. Further an intergate dielectric layer extends to the side walls of the floating gate allowing more area and a higher coupling ratio. A lower voltage may therefore be applied to the control gate. During an erasing operation the path of electrons can be redirected toward the substrate. Deterioration of a tunneling insulating layer is thereby reduced or eliminated.

Abstract: A process for preparing an 1,3-alkanediol through carbonylation of an epoxide derivative includes the steps of (a) reacting an epoxide derivative with alcohol and carbon monoxide in a solvent at a temperature from about 30 to about 150° C. and at a pressure from about 50 to about 3000 psig in the presence of a catalyst system including an effective amount of a cobalt catalyst and an effective amount of a promoter to afford a reaction mixture including a 3-hydroxyester or derivative thereof in an amount of from 2 to about 95% by weight, (b) separating the reaction product and solvent from the catalyst and promoter, (c) reacting said reaction product and solvent with hydrogen at a temperature from about 30 to about 350° C. and at a pressure from about 50 to about 5000 psig in the presence of a catalyst system for hydrogenation to prepare a hydrogenation product mixture including a 1,3-alkanediol, and (d) recovering the 1,3-alkanediol from the hydrogenation product mixture.

Abstract: A ferroelectric capacitor with a ferroelectric film having a relatively larger amount of titanium constituent than zirconate constituent improves ferroelectric characteristics. The method for fabricating the ferroelectric capacitor includes the step of performing a heat treatment in an oxygen atmosphere after forming a contact opening in an insulating layer which covers an already formed ferroelectric capacitor. This heat treatment in an oxygen atmosphere can minimize undesirable side effects resulting from a platinum electrode oxidizing the ferroelectric film components.

Abstract: A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

Abstract: A method for fabricating a semiconductor device to reduce the contact resistance by enhancing the surface concentration of doped polysilicon in a semiconductor substrate divided into active and field regions, comprises the steps of forming a plurality of word lines each having a cap insulating layer with a predetermined interval between adjacent word lines on the substrate, forming source/drain impurity regions in the active regions adjacent to both sides of each of the word lines, forming insulating sidewalls on both sides of each of the word lines, forming capacitor node plugs and bit line contact plugs on the source/drain impurity regions, forming a plurality of bit lines in the direction perpendicular to the word lines with a predetermined interval between adjacent bit lines by forming bit line contact holes contacting the bit line contact plugs in a first insulating interlayer deposited on the substrate, forming storage electrode contact holes to expose the capacitor node plugs in a second insulating int

Abstract: In a semiconductor manufacturing method, etching control is provided by introducing a material containing a material having at least one of an —H, —C, —CH, —CH2, and —CH3 radical component, e.g., Si—O—C, in a lower portion or layer of a dielectric layer formed during a semiconductor manufacturing process. A semiconductor device made by the method includes a first dielectric layer of a material having a given amount of carbon formed on the semiconductor substrate, and a second dielectric layer of a material having a lesser amount of carbon formed on said first dielectric layer wherein the second dielectric layer has an etched pattern formed by etching the second dielectric layer to a depth determined by etching resistance of first dielectric layer.