Abstract: A semiconductor memory device is provided that includes a plurality of normal memory cells, a device for activating the memory cells in response to an externally applied address and a plurality of redundant memory cells. A memory and comparison device may include a device for storing an address of a failed memory cell existing within a plurality of normal memory cells and a device for comparing the externally applied address with the failed memory cell address. A redundant memory cell selection device may select any one of a plurality of redundant memory cells in response to an output signal output from the memory and comparison device. A redundant memory cell activating device may activate the redundant memory cell, responsive to an output of the memory and comparison device.

Abstract: A method and apparatus for demodulating includes differential-detecting an input signal into which a unique word is inserted, correlating an output of the differential-detection and a data table obtained by differential-detecting the unique word, detecting a time when an electric power of a correlation output which exceeds a threshold value becomes the local maximum, reading the input signal stored in a buffer from the leading end of the unique word, estimating a frequency error of the input signal based on a phase of the correlation output, obtaining a signal by removing the frequency error from the read signal and inverse-modulating a unique word portion in the signal in which the frequency error has been removed, according to a data of a unique word table, and then reproducing a carrier signal.

Abstract: A portable printing device including: a case; a print unit having a print head with a print surface, the print head being switchable between a raised position and a lowered position with respect to the case; and a shutter member that covers the print surface of the print head when the print head is in its raised position. A link mechanism including crossed arms is provided for freely pivotably supporting the print unit with respect to the case.

Abstract: This invention relates to a system and method for altering the harmonic referent of segments of a music composition while maintaining conformity to a harmonic rule-base. It enables one to make changes to the harmonic referent (i.e. chord progression) underlying a segment of music, which causes a change in the pitches within that segment so that the pitches are have a compatible analysis within the new chord progression. The invention can advantageously preserves the harmonic function of each pitch in the segment, while changing the harmonic content of the passage. Further, the invention can preserve the shape of a melody line during such a transformation.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion, a sub memory portion composed of a plurality of memory cell groups and a bi-directional data transfer circuit provided between the main memory portion and the sub memory portion, wherein power source voltages of the main memory portion and the sub memory portion are different from each other. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A description is given of an electronic auction machine, which reacts to changing sales conditions with appropriately adjusted machine prices. For existing automatic vending machines restocking is based upon very vague experience figures and in particular customary fluctuations in sales are not taken into consideration. With the proposed machine, using a computer current market data are recorded (31) and using these data the current market situation is automatically assessed (32,34). A corresponding updated machine price (33,35) is then displayed.

Abstract: A semiconductor storage device having a plurality of banks therein, includes a main drive circuit (hereinafter referred to as a main SAPN circuit), provided for each bank, for driving a sense amplifier and an auxiliary drive circuit (hereinafter referred to as a sub-SAPN circuit) for holding electric potential after driving the sense amplifier. The main SAPN circuit of each bank is commonly connected to a VDD wiring and a GND wiring (hereinafter referred to as a main power-supply wiring), the sub-SAPN circuit of each bank is connected to each of the VDD wiring and the GND wiring which are provided for each bank and smaller in capacity than the main power-supply wiring, and after completion of a sensing operation by the sense amplifier of each bank, only the sub-SAPN circuit is set in an active state to hold electric potential of the sense amplifier.

Abstract: An IC package suitable for high density mounting and high speed is provided, by improving the humidity resistance and mounting stress resistance at a resin-sealed type BGA package and improving the reliability lessened a warp of the package. A concave part is provided in a multi-layer wiring substrate which has an exhaling route of water vapor expanded by heat in the inside of the package and a semiconductor chip is mounted at the concave part and is connected electrically to the substrate and the upper surface and sides of the package is sealed with resin. By this constitution, the infiltration of water is prevented and the stress at receiving thermal stress is lessened and the occurrence of stripping and crack of the inside of the package is prevented. Moreover, by utilizing the concave part effectively and connecting electrically, the wiring length is shortened and the high frequency characteristic is improved.

Abstract: A semiconductive memory device has a plurality of memory cells and writing data in a specific one of the memory cells in accordance with a write-in address. The semiconductive memory device comprises a control signal producing section for producing a plurality of control signals in accordance with a synchronous signal. The control signals have phases different from one another. A column selection signal producing section is responsive to the write-in address and the control signals for producing a plurality of column selection signals. A latch section is for latching the data as latched data in synchronism with the control signals. A write bus section supplies the latched data to the memory cells. A write-in section writes the latched data on the write bus means in the specific memory cell in accordance with the column selection signals.

Abstract: An objective lens for an optical disc includes a positive single lens, disposed between a light source and the optical disc. The objective lens has a first surface directed to the light source and a second surface directed to the optical disc. The first surface has a convex shape and both the first surface and the second surface are aspheric. The objective lens satisfies the following condition: 1.0<.vertline.R2/R1.vertline.<1.2, where R1 is the paraxial radius of curvature on the light source side surface and R2 is the paraxial radius of curvature on the optical disc side surface.

Abstract: Output current of light receiving element Dph is converted into a voltage by a core amplification section, and the voltage output is extracted as an amplification output through an outputting circuit section. The output voltage is fed back to the base of transistor T2 of a differential circuit of the core amplification section, by which it is compared with base reference voltage Vref of transistor T1. When the input current is low, the gain of the core amplification section is dominated by the product of the current flowing through transistor T2 and resistor R4, but when the input current is high, the gain is dominated by the product of current flowing through transistor T1 and resistor R3. Consequently, if resistor R3 is set lower than resistor R4, then when the input current is high, the gain margin indicating a degree of stability of the feedback circuit can be made large, and this stabilizes operation of the front-end amplification circuit.

Abstract: The present invention enables non-musicians to effectively compose music using a computer, and provides them with the means to manipulate musical content in an intuitive fashion without the need for formal musical training. The invention combines a representation of musical knowledge with a representation of musical data in such a way that permits transposition of the data to be constrained to conform to a set of harmonic rules. The user can select pitches to be moved higher or lower, and a system insures that it sounds good (where good is defined to mean "satisfies the conditions of the harmonic rule base").

Abstract: A power-on reset circuit comprises an oscillation circuit, an oscillation end detection circuit, a voltage stabilizer for generating a predetermined voltage (VDD2) from a power-supply voltage (VDD), and a start-up circuit. The power-on reset circuit further comprises a latched circuit. While the power is rising, the latched circuit becomes of an initial state and outputs a signal for arranging the latched circuit to a power-on reset state. When a value of the VDD becomes more than the value of the VDD2, by which the VDD2 becomes of a stable state, the initial state of the latched circuit is canceled, while as the VDD becomes stable, the oscillation circuit starts the oscillation in order to arrange the latched circuit to a set state, thus outputting a signal for canceling the power-on reset state.

Abstract: A checkerboard data pattern is written in a semiconductor memory with a simple arrangement. First, memory cell transistors M00-M77 are erased. A test signal TS is turned to "L," an address ax0 to "1," write signals D0, D2, D4 and D6 to "1." This causes "1" to be written in the memory cell transistors even-numbered in both the rows and columns. Then, the test signal TS is turned to "L," an X address ax0 to "0," write signals D1, D3, D5 and D7 to "1." This causes "1" to be written in the memory cell transistors odd-numbered in both the rows and columns. Thus, the checkerboard can be written with a simple arrangement by activating only the least significant bit ax0 of X addresses ax2-ax0.

Abstract: In an input circuit of a semiconductor device, a CMOS inverter has first and second transistors connected in series between an external power supply and ground and complementarily operating in accordance with an input signal. The first and second transistors have a connection point connected to an output terminal. A first switching device is connected in parallel to the second transistor and turned on/off. A comparator compares a voltage from the external power supply with a predetermined reference voltage and outputs a reference signal representing a comparison result. A logic circuit performs a logical operation between the reference signal from the comparator and the input signal supplied to an input terminal of the CMOS inverter and ON/OFF-controls the first switching device on the basis of a logical operation result.

Abstract: A main word driver, a main word driver for redundancy and a memory array are adjacent to each other and are arranged in a column or a row direction. Plural pairs of these are arranged in row and column directions and a block is constructed with plural memory arrays arranged in the column direction as a unit. A divisional driver control circuit is arranged in each column of each memory array. A sense amplifier is arranged between respective memory arrays in a row. A data amplifier is arranged with respect to each block. A main word signal for redundancy RMWL' as one output of the main word driver for redundancy within each block is also used as a block selecting signal showing selective activation in a block unit through a block selecting circuit BSL. Thus, it is possible to reduce a layout area of the semiconductor memory device in a divisional word driver system.

Abstract: This invention discloses a methodology for controlling a manufacturing process using an effective optimal experimental design for enabling a manufacturing engineer to determine process status and proper setpoints for all process parameters. The method is optimal, in a sense of requiring a smallest set of measurements which can capture all main effects and all their interactions.

Abstract: A storage device has a relative address table. An address is sequentially generated by an address adder based on a start address and a plurality of relative addresses held in the relative address table. When a pattern of the address is unchanged, a succeeding access is processed without resetting the relative addresses in the relative address table.