Abstract: A system, apparatus, and method for filling a display panel having first and second plates, with liquid crystal material, includes a nozzle for depositing a layer of liquid crystal material over a surface of a first plate of the panel, a scanning arm, coupled to the nozzle, for uniformly forming the layer of liquid crystal material over the surface of the first plate of the panel, and an attachment mechanism for placing the second plate over the first plate having the liquid crystal material thereover, thereby to form the display panel.
Type:
Grant
Filed:
May 11, 1998
Date of Patent:
April 25, 2000
Assignee:
International Business Machines Corporation
Inventors:
Robert Jacob von Gutfeld, Shui-Chih Alan Lien
Abstract: A partial oxide film on a base region is removed to form an opening, a polycrystalline silicon film is deposited directly thereon, and by dry etching, the polycrystalline silicon film is divided into a region including an impurity of same conductive type as the base, and a region including an impurity of reverse conductive type of the base. By heat treatment, the impurity is diffused from the polycrystalline silicon film into the base region, and an external base diffusion layer and an emitter diffusion layer are formed. In succession, the surface of the polycrystalline silicon film is formed into polyside film to lower the resistance, and by using the polycrystalline silicon film as emitter electrode and base electrode, a fine base and emitter area is realized.
Abstract: IP based networks use a number of different IP routing protocols to determine how packets ought to be routed. However, due to the rapid growth of the Internet, there is a great need for higher packet forwarding performance. This invention describes a way to map IP routing information onto a technology that uses label switching and swapping, such as ATM, without the need to change the network paradigm. This allows a network to continue to function and appear as a standard IP network, but with much higher performance. In this invention, an Integrated Switch Router (ISR), is a switch that has been augmented with standard IP routing support. The ISR at an entry point to the switching environment performs standard IP forwarding of datagrams, but the "next hop" of the IP forwarding table has been extended to include a reference to a switched path (for example, the VCC in ATM technology).
Type:
Grant
Filed:
September 30, 1997
Date of Patent:
April 25, 2000
Assignee:
International Business Machines Corporation
Inventors:
Nancy Karen Feldman, Arun Viswanathan, Richard M. Woundy, Richard H. Boivie
Abstract: A method for accommodating electronic commerce in a communication network capacity market. The method includes the steps of identifying a plurality of players in the communication network capacity market, each of which players can solicit capacity in communication network capacity market; providing a neutral third-party, the neutral third party and the plurality of players configured in a hub arrangement for communicating with each of the plurality of players in communication network capacity trades; and, realizing an open market conditionality between each of the plurality of players and the neutral third party so that the communication network capacity supplied by one or more of the players can be bought and sold among the players; and, the neutral third party can preserve anonymity of each of the plurality of players soliciting communication network capacity.
Type:
Grant
Filed:
December 11, 1997
Date of Patent:
April 25, 2000
Assignee:
International Business Machines Corporation
Abstract: To increase access speed, a moving image communication system includes a transmitter for outputting a packet including a predetermined number of subpackets containing a first information and a second information, and a receiver for receiving the packet. The receiver includes a memory for storing the first information, a counter for counting a number of the first information read out from the memory, an image processor for receiving the first information from the memory, and for generating an output signal of the receiver based on the first information, and a controller for controlling the image processor to output the output signal, when the counter counts the predetermined number.
Abstract: A surface acoustic wave filter includes IDTs on an input side and on an output side, the Inter Digital Transducers (IDTs) are formed by depositing a thin film made of aluminum and the like on a piezoelectric substrate made of crystal, and disposed on the substrate with a spacing interposed therebetween. The width of each electrode digit of each IDT is 1/4 of the wavelength of the surface acoustic wave during resonance. A reflection coefficient .epsilon. per electrode digit and the total number N of pairs of the electrode digits constituting the IDTs on the input side and on the output side are set to satisfy N.epsilon..gtoreq.0.55. Also, the aperture width W.lambda. of a surface acoustic wave transmission path, the center frequency of the filter f in units of Hertz , and the thickness of the electrode digits H in units of meters, are set to satisfy fH.ltoreq.-17.5W+210.
Abstract: In lubricant (5) of a magnetic recording medium made of conventional perfluoropolyether, one or more conductive high molecular compound is mixed. The conductive lubricant (5) prevents electric charge generated by frictional electricity from staying on the medium surface, and effectively prolongs the head-life by suppressing the break of the head element because of electric discharge between the disk medium and the head element. By employing the conductive lubricant, magnetic recording media and magnetic recording devices which are more reliable and durable can be realized.
Abstract: A method and structure for disconnecting shorted bitlines from a dynamic random access memory circuit includes supplying a precharge voltage to equalization lines in the integrated circuit, supplying a negative voltage to wordlines in the integrated circuit, activating equalization devices connected to the bitlines and the equalization lines and maintaining the precharge voltage and the negative voltage until a short between one of the bitlines and one of the wordlines causes a corresponding equalization device of the equalization devices to have a permanently elevated threshold voltage.
Type:
Grant
Filed:
February 3, 1999
Date of Patent:
April 11, 2000
Assignee:
International Business Machines Corporation
Inventors:
Louis L. C. Hsu, Giuseppe La Rosa, Jack A. Mandelman
Abstract: A semiconductor device includes a bias circuit for applying a bias to a transistor in which the semiconductor comprises a two-terminal element, connected between an external power source and at least an input of the transistor, having a first conductive contact layer connected to the input of the transistor, a second conductive contact layer connected to the external power source, and a semiconductor layer having a semi-insulation intervened between the first and second conductive contact layers, thereby reducing the thermal runaway caused by temperature rise.
Abstract: In a demodulating device which comprises an orthogonal transforming circuit, an up-converting circuit, a pulse signal producing circuit, and a low-pass filter, the orthogonal transforming circuit orthogonally transforms a received frequency shift keying signal to produce a first base band signal and a second base band signal. A phase converting circuit converts a clock signal from a clock signal producing circuit to produce a first clock signal having a first phase and a second clock signal having a second phase. A first EXOR circuit receives the first base band signal and the first clock signal to produce a first EXOR output signal. A second EXOR circuit receives the second base band signal and the second clock signal to produce a second EXOR output signal. A mixing circuit mixes the first EXOR output signal and the second EXOR output signal to produce and supply an up-converted signal to the pulse signal producing circuit.
Abstract: To provide a semiconductor device including a self-align type multi-emitter bipolar transistor wherein every collector-base isolation length can be reduced into a minimum value allowed in connection with the collector-base breakdown voltage, in a self-align type bipolar transistor having a multi-emitter structure, more than one emitter/base formation regions (114 and 115) and at least one collector leading region (106) are arranged in a single array, and extrinsic base regions (114) are connected to at least one base electrode (119c) having a contact plug (118c) provided outside the single array by way of a base leading electrode (109). Therefore, collector-base isolation lengths can be set to be a minimum length (e) determined by a collector-base breakdown voltage, enabling to minimize the collector resistance, the collector-base capacitance and the collector-substrate capacitance, as well as to minimize the element size of the bipolar transistor.
Abstract: In order to clip the levels of an incoming in-phase and quadrature signals, a comparator receives the in-phase signal, a clipping level, and an inverted clipping level. The comparator compares the level of the in-phase signal with each of the clipping level and the inverted clipping level, and generates a comparison result. A selector, in response to the comparison result, allows the in-phase signal to pass therethrough when the level of the in-phase signal exceeds the inverted clipping level and less than the clipping level, selecting the inverted clipping level when the level of the in-phase signal is less than the inverted clipping level, and selecting the clipping level when the level of the in-phase signal exceeds the clipping level. On the other hand, the level of the quadrature signal is limited using another comparator and selector in exactly the same manner as mentioned above.
Abstract: A fault simulation method for simulating an entire circuit represented by a gate model, comprises the steps of preparing a plurality of fault circuits represented by gate models, which are equal in number to the number of internal faults, with the internal faults assumed in the entire circuit, of dividing each of the fault circuits into a plurality of partial circuits each of which is represented by the gate model, of replacing internal faults in the partial circuits with external faults out of the partial circuits that are equivalent to the internal faults; of translating the partial circuits into translated partial circuits represented by superior models which have operation speed faster than that of the gate models, and of simultaneously simulating both of a good circuit represented by the superior model and the fault circuits represented by the superior models to determine whether or not the internal faults can be detected by comparing results of simulations.
Abstract: A double-chuck mechanical pencil has an outer tube, a tip fitting provided in the front of the outer tube, a tip chuck located at the tip of the tip fitting for holding a writing substance (e.g., a lead) and urged rearward in the axial directed, and a delivery chuck for delivering the lead. At least one of the tip chuck and the delivery chuck is formed of a synthetic resin material including polyoxymethylene.
Abstract: A high-speed delay verification apparatus and method includes a tracing device for respectively tracing a circuit in input (fan-in) and output (fan-out) directions thereof, based on the circuit information stored in a delay model storage device. The tracing device obtains the maximum value of the delay time of each node. The tracing device further sums the maximum values of the delay times obtained, and adds the sum of the maximum value of the delay time obtained for each node to circuit information of the delay model storage device to store it into an additional model storing device. A limit inspecting device deletes, based on the information stored in the additional model storing device, the node and its arc in which the sum of the maximum value of the delay time is less than the limit value of the delay time of the limit value storing device from the information stored in the additional model storing device and then stores such node and arc information in a modified model storage device.
Abstract: A CML-CMOS conversion circuit according to this invention includes: a differential circuit in which resistance is connected as load; a first current mirror circuit made up from an n-channel MOS transistor connected to one output of the differential circuit; a second current mirror circuit made up from an n-channel MOS transistor connected to the other output of the differential circuit; a third current mirror circuit made up of two p-channel MOS transistors connected in series to the first current mirror circuit and the second current mirror circuit; and a CMOS inverter that takes as input the output signal of the second current mirror circuit and that outputs a signal at CMOS logic amplitude.
Abstract: A handy printing device comprises a printing unit that forms images on a print medium in consecutive scan lines resulting from scanning relative movement between the printing unit and the print medium: a movement amount detection unit that detects amount of relative movement between the printing unit and the print medium; an interface that receives print data from an external source; a received data memory that stores the print data received by the interface; a print data extraction unit that extracts, from the print data stored in the received data memory, print data to be printed by the printing unit in a single scan line; and a print control unit that controls the printing unit to print the single scan line based on detection by the movement amount detection unit and on the print data extracted by the print data extraction unit.