Patents Represented by Attorney McGinn & Gibb, PLLC
  • Patent number: 6853421
    Abstract: In a transflective type LCD provided with a transparent region and a reflection region in each pixel, when an irregular film 11 is formed on an active matrix substrate 12 to form irregularities of a reflection electrode film 6, the irregular film 11 is specifically formed to almost the same film thickness in both the transparent region and the reflection region to provide substantially the same inter-substrate gap in these two regions so that they may have almost the same V-T characteristics and also the reflection electrode film 6 made of Al/Mo is formed so as to overlap with a transmission electrode film 5 made of ITO all around an outer periphery of the transmission electrode film 5 by a width of at least 2 ?m, thus suppressing electric erosion from occurring between the ITO and Al substances at the edge of the transmission electrode film 5.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: February 8, 2005
    Assignees: NEC Corporation, NEC LCD Technologies, Ltd.
    Inventors: Michiaki Sakamoto, Satoshi Ihida, Hidenori Ikeno, Masaki Shinohara, Shigeru Kimura, Kenji Morio, Kazurou Saeki
  • Patent number: 6851081
    Abstract: A semiconductor memory device having an error check and correction (ECC) type error recovery circuit in which disposition of ECC cells is improved. The memory device comprises: a memory cell array including a plurality of normal cell array portions and an ECC cell array portion; an X decoder for selecting one of word lines in the memory cell array, the word lines extending from the X decoder to the memory cell array; an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, the cell data including data from normal cells and ECC cells of the selected word line. The ECC memory cell array portion is disposed at a location other than the far end of the word lines from the X decoder, that is, the ECC cell array portion is disposed at a location in which read out speed of data from ECC cell or cells does not become the worst speed in the memory device. Therefore, the worst data read out speed can be measured from outside.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: February 1, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Kouji Yamamoto
  • Patent number: 6849884
    Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: February 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, David M. Fried, Louis D. Lanzerotti, Edward J. Nowak
  • Patent number: 6850904
    Abstract: A method and structure for forecasting financial obligations for processing mask orders for semiconductor chips includes preparing a relational database of part numbers of graphical data and common mask order descriptions, processing a mask order through the relational database to output part numbers, predicting costs of manufacturing a mask associated with the mask order, and altering aspects of the mask order to produce a change on the costs of manufacturing the mask.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: February 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ballas, Jeanne P. S. Bickford, Thomas R. Maheux, Paul G. McLaughlin, Donald L. Poulin
  • Patent number: 6850090
    Abstract: Provided is a level shifter including: a first level shifter circuit having first and second transistors whose sources are applied with a power source voltage and drains are connected with gates of the other transistors, and third and fourth transistors whose gates are applied with input and inverted signals, drains are connected with the drains of the first and second transistors, and sources are grounded; and a second level shifter circuit having fifth and sixth transistors whose sources are grounded and drains are connected with gates of the other transistors, and seventh and eighth transistors whose sources are applied with the power source voltage, gates are applied with the input and inverted signals, and drains are connected with the drains of the fifth and sixth transistors, the drains of the first and fifth transistors and the drains of the second and eighth transistors being connected with each other, respectively.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 1, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Junichi Aoki
  • Patent number: 6848555
    Abstract: An electronic controlled coupling including a wet-type multiple disc clutch, a coupling case, a hydraulic chamber, an oil pump, an electric motor, an electric control unit, and a supply passage for supplying hydraulic pressure. The coupling case accommodates the wet-type multiple disc clutch and contains oil. The oil pump driven by the electric motor is connected to the coupling case. The outlet of the oil pump is connected to the hydraulic chamber of the wet-type multiple disc clutch with the supply passage therebetween. The electric control unit controls the speed of rotation of the electric motor through a motor driver so that the pump discharge pressure is equal to an operating pressure required for the wet-type multiple disc clutch. The electronic controlled coupling performs a complete coupling mechanism increasing the durability as a coupling and a compact and simple structure enhancing the flexibility in designing.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: February 1, 2005
    Assignees: Koyo Seiko Co., Ltd., Fuji Jukogyo Kabushiki Kaisha
    Inventors: Takatoshi Sakata, Kouji Yoshinami, Kazuo Kanazawa, Mamoru Murakami
  • Patent number: 6849384
    Abstract: Photoacid generators comprising sulfonium salt compounds represented by the following general formula (2) wherein R1 and R2 represent each an alkyl group optionally having oxo, or R1 and R2 may be cyclized together to form an alkylene group optionally having oxo; R3, R4 and R5 represent each hydrogen or a linear, branched, monocyclic, polycyclic or crosslinked cyclic alkyl group; and Y? represents a counter ion.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: February 1, 2005
    Assignee: NEC Corporation
    Inventors: Shigeyuki Iwasa, Katsumi Maeda, Kaichiro Nakano, Etsuo Hasegawa
  • Patent number: 6851030
    Abstract: A method and structure for balancing associative resource (e.g., cache lines or buffers) allocation with respect to load, wherein said resources are allocated/deallocated to requesting processes or “agents” based on their reference history and demand. User agents that fail to meet minimum use criteria, are forced to relinquish logically allocated resources to high demand agents. Otherwise, an agent maintains control of its resources in the presence of other high demand agents, without cross-agent thrashing for resources. An associative resource “pool” is logically divided into m partitions. A small “partition reference” counter is employed for each partition to record its usage history. A global “persistence reference” counter functions to erase the “set reference” counter history at a programmable rate. Low “partition reference” counter values imply low usage, and make partition resources available to high usage partition(s) when needed.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: February 1, 2005
    Assignee: International Business Machines Corporation
    Inventor: Robert B Tremaine
  • Patent number: 6849970
    Abstract: A linear motor includes a plurality of electromagnetic coils continuously arranged and a magnet assembly disposed such that it may travel due to the interaction between itself and the magnetic fluxes from the coils. The coils include U, V, and W phase coils in star connection. The coils of the individual phases are installed in series around a hollow-shaft center core over the travel range of the magnet assembly such that the magnetic pole axis thereof is oriented in the same direction as the axis of the center core. The magnet assembly has an annular shape so that it may surround the coils, and is formed of a plurality of permanent magnets. The magnets are combined in series such that the same magnetic poles oppose each other and the magnetic pole axis is oriented in the same direction as the axis of the center core.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: February 1, 2005
    Assignee: Chronofang Co., Ltd.
    Inventor: Koji Watanabe
  • Patent number: 6847743
    Abstract: A polarization scrambler unit includes a plurality of polarization scramblers, a switching unit for coupling one of the polarization scramblers to a transmission line fiber, a detection unit for detecting an output signal from the polarization scrambler coupled to the transmission line fiber, and a controlling unit for switching, via the switching unit, between the polarization scramblers and another polarization scrambler whenever a false output signal is detected by the detection unit. Thus, the polarization scrambler unit has a redundant structure.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: January 25, 2005
    Assignee: NEC Corporation
    Inventor: Shohei Yamaguchi
  • Patent number: 6847203
    Abstract: Disclosed is an integrated circuit chip test apparatus that has a module test fixture having contact pads that are adapted to make contact with signal input/output pins on an integrated circuit chip being tested. An intermediate banking box is connected to the module text fixture and a tester is connected to the intermediate banking box. The tester includes at least one bank of channels there are more pins on the integrated circuit chip than there are channels in the tester. The intermediate banking box includes switches that are connected between the contact pads and the channels. The switches are adapted to selectively connect a subset of the contact pads to the channels to connect the tester to a subset of pins, thereby allowing the tester to test a portion of the integrated circuit that corresponds to the subset of pins.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: January 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Dennis R. Conti, John Lafferty
  • Patent number: 6847315
    Abstract: A method and structure stores and/or transmits and receives data in compressed form. Retrieval latencies are reduced by selectively transmitting a portion of the data in uncompressed form. When the apparatus is part of a computer architecture supporting main memory compression, a selected L2 cache line belonging to the unit of main memory compression is kept uncompressed. To minimize decompression latency, the uncompressed L2 cache line is stored with the compressed-memory directory. Alternatively, the uncompressed L2 cache line is stored in the compressed memory together with the rest of the memory compression unit it belongs to.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: January 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Vittorio Castelli, Peter A. Franaszek
  • Patent number: 6846741
    Abstract: A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: January 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Robert M. Geffken, Anthony K. Stamper
  • Patent number: 6845426
    Abstract: A disk array controller prevents a cache page conflicts between a plurality of commands issued from the same host. A disk array controller 10 includes host directors 161 and 162, which are provided for hosts 121 and 122, one for each, and which controls I/O requests from the hosts 121 and 122 to execute input/output to or from disk drives 141 and 142, and a shared memory 18 shared by the host directors 161 and 162 and forming a disk cache. When the host 121 issues a plurality of read commands to the same cache page, the host director 161 starts a plurality of data transfers while occupying the cache page during processing of said plurality of read commands.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: January 18, 2005
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Patent number: 6844246
    Abstract: A GaN layer 32 grows in vertical direction on a GaN layer 31 where neither a first mask 41m nor a second mask 42m is formed. When thickness of the GaN layer 32 becomes larger than that of the first mask 41m, it began to grown in lateral direction so as to cover the first mask 41m. Because the second mask 42m is not formed on the upper portion of the first mask 41m, the GaN layer 32 grows in vertical direction. On the contrary, at the upper region of the GaN layer 31 where the mask 41m is not formed, the second mask 42m is formed like eaves, the growth of the GaN layer 32 stops and threading dislocations propagated with vertical growth also stops there. The GaN layer 32 grows in vertical direction so as to penetrate the region where neither the first mask 41m nor the second mask 42m is formed. When the height of the GaN layer 32 becomes larger than that of the second mask 42m, the GaN layer 32 begins to grow in lateral direction again and covers the second mask 42m.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: January 18, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Kazuyoshi Tomita, Masahito Kodama
  • Patent number: 6845192
    Abstract: An optical amplifying and relaying system capable of easily and highly accurately monitor troubles in optical amplifiers provided in an up and a down optical fiber transmission line opposing each other is disclosed. Monitoring light signal folding-back lines including variable optical attenuators 4a and 4b and wavelength selective reflecting means 5a and 5b, respectively, are provided between optical transmission lines L1 and L2, which oppose each other and on which optical amplifiers 4a and 4b are disposed each other.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: January 18, 2005
    Assignee: NEC Corporation
    Inventors: Ryu Yokoyama, Takaaki Ogata
  • Patent number: 6843893
    Abstract: A method and structure for an apparatus for removing metal from an integrated circuit structure is disclosed. A container holds an integrated circuit structure that has a metal portion. An electronic device connected to the container produces an electronic field proximate to a limited region of the metal portion. A first supply connected to the container supplies an oxidizing agent within the container. A solvent supply connected to the container supplies solvent to the limited region of the metal portion.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: January 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Steven B. Herschbein, Herschel M. Marchman, Chad Rue, Michael R. Sievers
  • Patent number: 6841931
    Abstract: In an LED lamp, a Zener diode is mounted on a copper plate, and a GaN-based light-emitting element is mounted on the Zener diode with an electrode of the element being oriented facedown. Two Zener diodes close to the center of the LED lamp are mounted on a common copper plate, thereby interconnecting the two light-emitting elements in series. Consequently, a Zener diode is connected to the respective two Zener diodes by means of a wire serving as a conductive member. Four light-emitting elements are connected in series, so that four light-emitting elements are connected in series, thus completing a circuit configuration. In this way, use of the Zener diodes for interconnection purpose enables a reduction in the number of minimum required wires. It is better to connect the wire to the upper surfaces of the Zener diodes, thereby obviating a necessity for a redundant wire space and enabling miniaturization of the LED lamp.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: January 11, 2005
    Assignees: Toyoda Gosei Co., Ltd., Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuji Takahashi, Koichi Kaga, Hideaki Kato, Tadaaki Ikeda, Michio Miyawaki
  • Patent number: 6842783
    Abstract: A method and system for controlling and guaranteeing a service level agreement (SLA) based on a communications outbound link bandwidth usage to a plurality of customers having electronic business activity hosted by at least one server as a server farm, includes monitoring the outbound communications bandwidth usage by each customer traffic to determine a level of service being provided to each customer with respect to the agreed service level agreement in each service cycle time per unit of time. The flow of incoming requests to each customer business activity application is controlled so as to guarantee a level of service previously agreed to the customer by queuing requests to the customer and by selectively dropping requests to the customer to guarantee the agreed service levels to the customer. The controlling process controls and guarantees each outbound link usage based service level agreement by controlling the flow of incoming requests to the at least one server.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: January 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Richard Harold Boivie, Daniel Manuel Dias, Colin George Harrison, Eric M. Levy-Abegnoli, Jean A. Lorrain, Kiyoshi Maruyama, Pascal Pol Marie Thubert
  • Patent number: 6842274
    Abstract: A light scanner has a light source 1 of a two-dimensional array consisting of a plurality of light source elements, a coupling lens system 2 for collimating a light flux from the light source 1, a shaping lens system (cylindrical lens 4 and lens 5) for shaping the light flux, light beam deflection means 6 for deflecting and scanning the post-shaped light flux, and a scanning lens system 7 for forming an image of the deflected and scanned light flux on a scanned medium 8. Assuming that the focal length of the coupling lens system 2 is f, a slit 3 for limiting the subscanning direction width as a member for shielding a part of the light flux is placed at a location at a distance of about f from the coupling lens system 2 in an opposite direction to the light source 1.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: January 11, 2005
    Assignee: Hitachi Printing Solutions, Ltd.
    Inventors: Kazuhiro Akatsu, Takeshi Mochizuki