Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7863134
    Abstract: A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hirotaka Hamamura, Itaru Yanagi, Toshiyuki Mine
  • Patent number: 7864437
    Abstract: A microscope apparatus efficiently supplies and collects a liquid for observation by local liquid immersion. The apparatus includes an objective of a liquid immersion system, a discharging member for discharging the liquid between a front edge of the objective and a substrate, and a sucking member for sucking the liquid. Inclined faces are provided respectively in two positions adjacent to the front edge in the periphery of the objective, and protruded portions are provided in positions adjacent to the inclined faces. An aperture portion bounded by the protruded portions and the substrate is formed at the side face. The discharging member includes a tubular member provided on the inclined face for discharging the liquid. The sucking member includes another tubular member for sucking the liquid while taking in air via the aperture portion.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: January 4, 2011
    Assignee: Nikon Corporation
    Inventors: Manabu Komatsu, Toshio Uchikawa, Hiromasa Shibata
  • Patent number: 7864438
    Abstract: An image forming lens has a configuration that an image forming lens IL for receiving parallel beams of light emitted from an observation target object and emerging from an infinity-designed objective lens of a microscope and forming an image of the observation target object in a predetermined position, is constructed of, in order from an object side, a first lens group G1 having positive refractive power and a second lens group G2 having negative refractive power, and the first lens group is constructed of a positive lens (e.g., a biconvex lens L1) and a negative lens (e.g., a negative meniscus lens L2).
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: January 4, 2011
    Assignee: Nikon Corporation
    Inventor: Hiroaki Nakayama
  • Patent number: 7864414
    Abstract: Providing a microscope capable of movably adjusting an observation field of a sample without moving the sample. The microscope includes a first objective lens, a second objective lens, a mirror, an angular adjustment mechanism, and a shift mechanism. The first objective lens is disposed to the sample side. The second objective lens forms an intermediate image of the sample together with the first objective lens. The mirror is disposed with a tilt on an optical path between the first objective lens and the second objective lens. The angular adjustment mechanism rotatably adjust the mirror in the tilt direction. The shift mechanism makes a shift adjustment of the second objective lens in an axial direction of a rotation axis of the mirror. With the configuration, the observation field can be moved two-dimensionally by the angular adjustment mechanism.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 4, 2011
    Assignee: Nikon Corporation
    Inventors: Ichiro Sase, Shuji Toyoda
  • Patent number: 7861983
    Abstract: The invention relates to a cold-insulated fixed-point pipe support for a low-temperature pipeline which includes an insulating system arranged between an outer shell and a supportable low-temperature pipeline having solid thermal insulating material which thermally insulates the pipeline from the low-temperature environment. A rotation-preventing and displacement-preventing device prevents rotation and displacement of the thermal insulating material with respect to the pipeline and an outer shell. A fixed-point pipe support is adapted to be fitted and removed in a substantially radial direction over the pipeline, and has at least one division with respect to shape with a division plane thereof extending perpendicular to a cross-sectional plane, and having a connecting device for releasable connecting and fixing shaped parts formed by the division.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: January 4, 2011
    Assignee: Lisega Aktiengesellschaft
    Inventors: Heinz-Wilhelm Lange, Ashley Challenor
  • Patent number: 7865344
    Abstract: A method for creating a global simulation model of an architecture for models of integrated circuits under development, including reading an architecture description file of the global model and storing information related to all of the possible configurations instantiating the components and storing the corresponding information, topologically connecting the interface signals, physically connecting the interface signals, at the level of each instance of the components using a component and connection rule table, and storing the corresponding information, and automatically generating the HDL-type and HLL-type source files of the global simulation model.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: January 4, 2011
    Assignee: Bull S.A.
    Inventor: Andrzej Wozniak
  • Patent number: 7863652
    Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shunsuke Toyoshima, Kazuo Tanaka, Masaru Iwabuchi
  • Patent number: 7863127
    Abstract: After forming a first gate electrode and a second gate electrode on a semiconductor substrate, a silicon oxide film is formed to cover an n-channel MISFET forming region, and a p-channel MISFET forming region is exposed. Subsequently, after a first element supply film made of, for example, an aluminum oxide film is formed on the whole surface of the semiconductor substrate, a heat treatment is performed. By this means, a high-concentration HfAlO film and a low-concentration HfAlO film are formed by diffusing aluminum into the first insulating film just below the second gate electrode. Thereafter, by using a magnesium oxide film as a second element supply film, magnesium is diffused into the first insulating film just below the first gate electrode, thereby forming a high-concentration HfMgO film and a low-concentration HfMgO film.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Mise, Tetsu Morooka
  • Patent number: 7863107
    Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Tamimoto, Takumi Soba, Toru Ueguri, Kazuo Kudo
  • Patent number: 7863670
    Abstract: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Ishii, Takashi Hashimoto, Yoshiyuki Kawashima, Koichi Toba, Satoru Machida, Kozo Katayama, Kentaro Saito, Toshikazu Matsui
  • Patent number: 7859095
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 7859345
    Abstract: The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Kawamoto
  • Patent number: 7859889
    Abstract: In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Norifumi Kameshiro, Riichiro Takemura, Tomoyuki Ishii
  • Patent number: 7855590
    Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: December 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Kazuo Tanaka, Shunsuke Toyoshima, Takeo Toba
  • Patent number: 7852051
    Abstract: A current-limiting circuit for limiting switch-on currents or transients includes a switch, a diode, an inductance, an input with a first connection and second connection, and an output with a first connection and second connection. The second connection of the input is connected via the switch to the junction of an inductance and the anode of a diode and via the inductance to the second connection of the output. The cathode of the diode is connected to the first connection of the input and to the first connection of the output. The switch is preferably an electronic switch controlled to provide clocked current limitation.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: December 14, 2010
    Assignee: PULS GmbH
    Inventor: Bernhard Erdl
  • Patent number: 7850633
    Abstract: The present invention is directed to devices, systems and methods for removing undesirable materials from a sample fluid by contact with a second fluid. The sample fluid flows as a thin layer adjacent to, or between, concurrently flowing layers of the second fluid, without an intervening membrane. In various embodiments, a secondary separator is used to restrict the removal of desirable substances and effect the removal of undesirable substances from blood. The invention is useful in a variety of situations where a sample fluid is to be purified via a diffusion mechanism against an extractor fluid. Moreover, the invention may be used for the removal of components from a sample fluid that vary in size. When blood is the sample fluid, for example, this may include the removal of ‘small’ molecules, ‘middle’ molecules, macromolecules, macromolecular aggregates, and cells, from the blood sample to the extractor fluid.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: December 14, 2010
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Edward F. Leonard, Alan C. West, Nina C. Shapley, Zhongliang Tang
  • Patent number: 7849637
    Abstract: Embodiments of the present invention are directed to a fold-up scaffold system that includes multiple spaced vertical beams supported at one end on a floor of a building and scaffold sections extending across the vertical beams. The system also includes means at opposite ends of the scaffold sections for pivotally supporting the scaffold sections to the vertical beams and at least two air cylinders for each scaffold section connected between the scaffold sections and the vertical beams. In addition, each of the at least two air cylinders is adapted to be actuated between a lowered and a raised position, the scaffold sections being pivoted away from the vertical beams when the at least two air cylinders are actuated to the lowered position to provide a substantially horizontal surface and is positioned substantially vertically against the beam when the at least two air cylinders are actuated to the raised position.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: December 14, 2010
    Inventor: Erwin Lowe
  • Patent number: 7847347
    Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: December 7, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
  • Patent number: 7845796
    Abstract: A spectacle lens includes a multi-contact diffractive optical element formed on at least one surface of a overall lens system that is arranged from an object to a pupil, in which an apparent Abbe number Vd when the overall lens system including the multi-contact diffractive optical element is regarded as a single lens satisfies Vd>60 . . . (1).
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: December 7, 2010
    Assignee: Nikon Corporation
    Inventor: Kenzaburo Suzuki
  • Patent number: 7845172
    Abstract: A generating facility is provided for generating electricity from both solar and non-solar energy sources. The solar generating portion of the facility includes capability to directly generate electricity from solar insolation, or to store the solar energy in a tangible medium, including stored heat, or solar generating fuel. The generating facility is configured to generate electricity simultaneously from both solar and non-solar sources, as well a solely from immediate solar insolation and from solar energy stored in a tangible medium. Additionally, the solar generating capacity may be segregated; such that separate spectra of solar insolation are used to capture heat for steam turbine based electrical generation, capture light energy for photovoltaic based electrical generation, and to grow biomass to generate a solar fuel.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: December 7, 2010
    Assignee: BrightSource Energy, Inc.
    Inventor: Arnold J. Goldman