Abstract: A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side opposite to the one side of the semiconductor chip. The reduction in size of the semiconductor device can be attained.

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract: A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.

Abstract: The invention relates to a coupling device comprising a support substrate; a first layer arranged on the support substrate and comprising first patterns produced within the thickness of said first layer, said first patterns being arranged in parallel and periodic rows; a second layer arranged on the first layer and comprising second patterns passing through the thickness of said second layer, said second patterns being arranged in parallel and periodic rows. The direction of periodicity of the rows of the first patterns is perpendicular to the direction of periodicity of the rows of the second patterns. The rows of the first patterns extend over a distance greater than or equal to the wavelength in the void of the optical wave intended to be coupled. The first patterns have a width less than or equal to a tenth of the wavelength of the optical wave intended to be coupled, and the period of these patterns is between 50 nm and 1 ?m. The second patterns are arranged so as to form a periodic diffraction grating.

Abstract: A trench is formed so as to reach a p?-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: In order to have operations of a central system executed by a satellite system, a linking structure is located between the central system and the satellite system. The linking structure includes: a communications link between the central system and satellite system; a control card, in the central system, that places said operations in one or more data blocks; and a coupler, in the satellite system, that sends through the link to the control card at least one read command to which the control card responds by sending said data block or blocks through the link to the coupler.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: In a method for determining a compaction degree of a surface segment, the following steps are provided: passing over the deposited layer of the surface segment to be compacted, determining positional data of a position of the compacting machine, defining a current partial surface of the surface segment of the deposited layer, the current partial surface possibly consisting of a plurality of subsegments which have already been passed over, measuring and/or picking up parameters at the position of the compacting machine, and storing the parameters together with the position data, assigning the parameters to the current partial surface or to all subsegments of the current partial surface, computing, from the parameters, a current compaction degree for the current partial surface or each subsegment of the current partial surface.

Abstract: A surface inspection apparatus capable of acquiring scattered light intensity distribution information for each scattering azimuth angle, and detecting foreign matters and defects with high sensitivity. A concave mirror for condensation and another concave mirror for image formation are used to cope with a broad cubic angle. Since mirrors for condensation and image formation are used, a support for clamping the periphery of a lens is unnecessary, and an effective aperture area does not decrease. A plurality of azimuth-wise detection optical systems is disposed and reflected light at all azimuths can be detected by burying the entire periphery without calling for specific lens polishing. A light signal unification unit sums digital data from a particular system corresponding to a scattering azimuth designated in advance in the systems for improving an S/N ratio.

Abstract: The present invention concerns a storage method and system (1) comprising processing means (11) and storage resources (20, 100) containing firstly storage means (20) including at least one physical library (P201 to P20n) and secondly memory means (100) called a cache (100), in which the processing means (11) of the storage system (1), vis-à-vis the computer platforms (101 to 10n), emulate at least one virtual library (V201 to V20n) from at least one physical library (P201 to P20n) which the storage system has under its control, characterized in that the processing means (11) of the storage system (1) comprise a management module (30) responsible for emulation and managing priorities over time for accesses to the storage resources (20, 100) using the results of calculations of at least one cache activity index per determined periods of time, and of at least one cache occupancy rate at a given time.

Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

Abstract: In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.

Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.

Abstract: In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs.

Abstract: In an image display device comprising a display part configured with a plurality of pixels and a peripheral integrated circuit which controls the display part, the display device is provided on a support substrate which has high durability for the impact and the bending, the pixel circuit is configured with an organic semiconductor TFT, the peripheral integrated circuit is configured with a low-temperature poly Si-TFT, this peripheral integrated circuit is provided on a support substrate of the display device being removed the support substrate when being manufactured, and the pixel circuit and the peripheral integrated circuit are connected with the same wire layer.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: An exterior door handle for a motor vehicle, including an electromechanical locking system and a manually actuated handle part that can perform a lifting movement in order to open a door lock. The lifting movement of the handle part is subdivided, a device generating an increased actuation resistance and a switch electrically opening the door lock at the end of a first lifting distance. The handle part can travel an additional lifting distance beyond the first lifting distance in case the electric power supply is interrupted or the electric locking system breaks down, the additional lifting distance mechanically opening the door lock.

Abstract: The present invention provides a roller-type one-way clutch comprising an annular outer race provided at its inner periphery with a cam surface, an inner race spaced apart from the outer race in a radially inner diameter side and disposed coaxially with the outer race for a relative movement therewith and having an annular outer peripheral track surface, a plurality of rollers disposed between the outer race and the inner race and adapted to transmit torque between the outer peripheral track surface and the cam surface, a cage for holding the plurality of rollers, and a C-shaped annular spring for biasing the rollers, through the cage, toward engagement with the cam surface.

Abstract: In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided.