Abstract: An cradle 100 equipped with a projector commands the power supply to an electronic camera 200 that is mounted on the cradle 100 to be turned on and the display of a main liquid crystal display 201 to be turned off in response to an on signal from a projection switch 101. A CPU 131 (FIG. 2) is provided in the cradle 100, and the CPU 131 (FIG. 2) performs expansion processing on the image data transmitted to the cradle 100 from the electronic camera 200 if the image data is compressed. The CPU 131 (FIG. 2) of the cradle 100 performs resizing processing on the image data having been expanded according to a projection resolution of the projector unit and records the resized data in a memory card. The CPU 131 reads out the resized image data from the memory card and performs replay processing to project the image data via the projector unit.

Abstract: The variable gain amplifier includes a bias circuit (BC) 1, a matching circuit (MC) 2, a variable gain resistive feedback amplifier (FA) 3 and an output follower (EA) 4. The resistance values of the load resistance Rc and feedback resistance Rf are changed in cooperation. In a case of making the load resistance Rc a high resistance to set the low noise amplifier to a high gain, the feedback resistance Rf is also made a high resistance, the feedback time constant ?fb(c1)?2?·RfCbe/(1+gmRc) of the closed loop of the resistive negative feedback amplifier 3 becomes substantially constant, and then the amplifier has a gain small in frequency dependency over a wide bandwidth. In a case of making the load resistance Rc a low resistance to set the low noise amplifier to a low gain, the feedback resistance Rf is also made a low resistance. The feedback resistance Rf with the low resistance increases the negative feedback quantity, and thus the amplifier is set to a low gain.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A system and method for delivering radiation treatment to a moving target within a patient according to a preprogrammed treatment plan including determining a difference between a surrogate signal representing a physical characteristic associated with said patient's actual breathing pattern during radiation treatment delivery and a tracking signal representing a physical characteristic associated with said patient's expected breathing pattern during radiation treatment delivery, and regulating a speed of delivery of said radiation treatment based on said determined difference.

Abstract: A process for creating and managing pairs of asymmetrical cryptographic keys and/or certificates associated with the pairs of keys, each pair of keys and associated certificates being intended for an object managed by a computer system. The process includes creating an individual request for creating and/or certifying at least one pair of keys for an object of the system that lacks a pair of keys or a certificate for its pair of keys.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: The present invention provides a lock-up clutch mechanism for a torque converter, comprising a lock-up piston and a front cover opposed to the lock-up piston and wherein a friction material having a friction surface is secured to one of the lock-up piston and the front cover, and the friction surface includes an outer peripheral friction surface which is engaged at an initial stage of engagement between the lock-up piston and the front cover and an inner peripheral friction surface which is engaged upon tightening, and the outer peripheral friction surface has a taper with respect to the inner peripheral friction surface, and the inner peripheral friction surface and the outer peripheral friction surface are subjected to a cutting operation.

Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.

Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.

Abstract: A helmet is disclosed that includes a hinged chin guard and a hinged visor. The chin guard and the visor can each be independently raised or they can be raised together. That is, they can be rotated up and from in front of the face of a wearer of the helmet. A one-button release mechanism is provided on the chin guard to release detents that secure the chin guard to the cap body. The chin guard can lock into place when raised or lowered. The chin guard is adapted to rotate in a substantially elliptical trajectory about the sides and top of the cap body. The visor can be rotated through a series of ratchet positions and be removed from the helmet without tools and without removing the chin guard.

Abstract: A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

Abstract: A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

Abstract: The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

Abstract: In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.