Abstract: A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads.

Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.

Abstract: A system and method for providing visual feedback to a user of an exercise machine for gauging fitness progress of the user. The system provides a user of an exercise machine with a virtual competition in which the user competes against virtual competitors based on his past performances or those of other users, either as an individual or as a member of a team. The team may also be part of a league. For an individual competing against his own past performance(s), the system may raise the level of performance required to win the virtual competition, and may also lower the level of performance required if the user is not performing well on a particular day. For an individual competing against others in either real-time or against designated results, either as part of a team or a league, the system may reduce the isolation, disconnection, and tedium often experienced by users of cardiovascular exercise equipment and provide a social outlet.

Abstract: An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.

Abstract: An objective lens OL includes, in order from an object, a first lens group G1 having positive refractive power, a second lens group G2 having positive refractive power, a diffractive optical element GD forming a diffractive optical surface D thereon, and a third lens group G3 having negative refractive power. The first lens group G1 includes at least one cemented lens and the most object side surface thereof forms a concave surface facing the object. The second lens group G2 includes at least one cemented lens. The third lens group G3 includes at least one cemented negative lens. In the objective lens OL, a principal ray crosses an optical axis between the second lens group G2 and the third lens group G3, and in the diffractive optical element GD, the diffractive optical surface D is disposed in the vicinity of the position where the principal ray crosses the optical axis.

Abstract: A semiconductor device having a microcomputer chip and a plurality of high-speed memory chips and capable of making wiring lines of the memory chips equal in length is disclosed. The semiconductor device comprises a first wiring substrate, a microcomputer chip mounted over the first wiring substrate, a second wiring substrate disposed over the microcomputer chip, a plurality of first solder bumps for connecting the first and second wiring substrates with each other, and a plurality of second solder bumps as external terminals formed over a back surface of the wiring substrate. A first memory chip and a second memory chip, as high-speed memory chips, are stacked within the second wiring substrate, wiring of the first memory chip and that of the second memory chip are made equal in length within the second wiring substrate, and a completed package structure having the second wiring substrate is mounted over a completed package structure having the first wiring substrate.

Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Abstract: A packaged residential fire pump system for sprinkler protection of one- and two-family dwellings. The system independently provides sufficient water pressure, and volume, for a two sprinkler flow for a period of time. An existing domestic water supply is supplemented with a dead water storage tank. The system can be combined with hydraulically sized, or scheduled, system piping and sprinkler heads.

Abstract: A method and apparatus are provided for moulding an article by feeding molten plastics material into a metering cavity (16), feeding a predetermined quantity of the material from the metering cavity into a mould cavity via a transition passage (26) adjacent the mould cavity and urging the molten plastics material from the transition passage into the mould cavity with a working stroke of a packing piston (24), until the packing piston closes a port (28) defined between the transition passage and the mould cavity and a leading face (32) of the packing piston forms part of the peripheral wall of the mould. Less than ninety percent of the mould cavity is filled with the molten plastics material when the packing piston starts its working stroke and the packing piston starts its working stroke while molten plastics material is still being fed from the metering cavity.

Abstract: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

Abstract: A polarization converting element includes: a main body that is made from a transparent member; an incident section that is provided to the main body, and upon which light generated from a light source is incident; an annular reflecting section that is formed on the periphery of the incident section; and a polarization splitting section that is formed opposite to the annular reflecting section on the emission side of light incident upon the incident section. One polarized light component of the incident light passes through the main body and is emitted from the polarization splitting section. Another polarized light component of the incident light is reflected towards the annular reflecting section by the polarization splitting section, and is emitted from the polarization splitting section after having again been reflected by the annular reflecting section and having been converted into light of a same polarization component as the light of the one polarized light component.

Abstract: Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

Abstract: A method of synthesizing a heteroleptic, multiple metal-containing metallocyclic catalyst, particularly suited for asymmetric catalysis, comprising combining a plurality of plural functional group-containing, monodentate ligands of complementary chirality, said plural functional groups being tethered to each other by tethers in the presence of a scaffold-structural metal Ms or derivative thereof, wherein at least one functional group on each ligand combines to ligate Ms to form a bidentate, Ms centered ligand scaffold containing the remaining functional groups and combining said bidentate ligand scaffold with a catalytic metal Mc or derivative thereof whereby the remaining functional groups combine to ligate Mc, thereby forming said catalyst.

Abstract: A method for manufacturing a friction plate in which a plurality of frictional material segments are adhered to a substantially annular core plate. The method previously registers the frictional material segments to adhesion positions, and presses the core plate to which adhesive agent is applied and the frictional segments to perform temporary adhesion. Further, an apparatus for manufacturing a friction plate in which a plurality of frictional material segments are adhered to a substantially annular core plate. The apparatus comprises a member for registering the frictional material segments while holding the frictional material segments in a state arranged in the adhesion positions.

Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.

Abstract: The present invention is directed to provide a low-power-consumption wide-range RF signal processing unit having a small chip occupation area. A semiconductor integrated circuit has, on a semiconductor chip, a resonant circuit including a first capacitor having a capacitance which can be controlled by a first control signal of a first control terminal, and a gyrator for equivalently emulating an inductor by including a second capacitor having a capacitance which can be controlled by a second control signal of a second control terminal. The capacitance and the inductor form a parallel resonant circuit. At the time of changing parallel resonant frequency, the capacitances of the first and second capacitors are coordinately changed. The parallel resonant circuit is suitable for an active load which is connected to an output node of an amplifier.

Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.

Abstract: An AF dark field illumination device and an objective lens are moved in unity. A tissue sample in a Petri dish is illuminated by infrared light incident with an oblique angle from an LED light source. The casting of the infrared light causes scattered light from the tissue sample. A part of the scattered light passes through the objective lens, thereby forming a dark-field microscope image, which is captured by a CCD camera. The sharpness of the dark-field microscope image is dependent upon the position of the objective lens. The position of the objective lens at which the dark-field microscopic image exhibits the highest sharpness is determined to be the focus position.

Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

Abstract: In a wireless transmitter and receiver, a background calibration type analog-to-digital converter generally occupies a large area because of the phase compensating capacity of an op-amp included in a reference analog-to-digital conversion unit. Further, the calibration type analog-to-digital converter generally requires a sample and hold circuit to exclude influence of parasitic capacitance of wirings, thereby increasing power consumption. Digital calibration is performed by using, as a signal for calibration, an input signal of a digital-to-analog converter in a transmitter circuit of the wireless transmitter and receiver and inputting an output signal from the digital-to-analog converter to the analog-to-digital converter in the receiver circuit.