Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: Providing an imaging apparatus capable of efficiently using effective pixels of a solid-state imaging device, and securing excellent peripheral light quantity of an image even upon vibration reduction. The imaging apparatus comprising: a high zoom ratio zoom lens 2 including, in order from the object, a first positive group, a second negative group, a third group, a fourth group, and a fifth group, upon zooming the first through fourth groups are moved along an optical axis; an imaging device capturing an image formed by the lens 2; a detector detecting variation in an image position; a driver moving the imaging device substantially perpendicularly to the optical axis; a controller controlling the driver for correcting variation in the image position; and a shield with an aperture for limiting bundle of rays incident on the periphery of the most object side lens in the lens 2; and given condition is satisfied.

Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.

Abstract: An endoscopic device separates ingested food from gastric fluids or gastric fluids and digestive enzymes, to treat obesity. In a particular embodiment a gastric bypass stent comprises a tubular member and two or more stent members defining a lumen. The tubular member has a substantially liquid impervious coating or covering and one or more lateral openings to permit one-way liquid flow.

Abstract: A zoom optical system has a first lens group having a positive refracting power; a second lens group having a negative refracting power; a third lens group having a positive refracting power; a fourth lens group having a negative refracting power; and a fifth lens group having a positive refracting power, in the order from the object side. The fourth lens group is composed of a cemented lens of a negative lens and a positive lens in the order from the object side, and a condition of the following expression is satisfied: ?p>30.0, where ?p is an Abbe number of the positive lens.

Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.

Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

Abstract: The present invention provides a voltage-controlled oscillator operating from microwave frequencies to millimeter wave frequencies, which is capable of outputting a large power with an output impedance thereof being set up to a predetermined level at low power consumption, and a communication device using the same.

Abstract: In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p+ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.

Abstract: In a display control drive device that displays an image on a display device, a data transfer rate may vary depending on received image data because of a difference in an image size. Assuming that driving force with which a driver or an amplifier is driven is designed based on a maximum data transfer rate and the driver or amplifier is operated with the driving force, when the transfer rate is low, an unnecessary current is consumed. According to the present invention, a display control drive device sequentially reads display data from a display memory in which the display data is stored, produces three primary color image signals that are applied to pixel locations in a dot-matrix color display device, and transmits the signals through a common external output terminal in a time-sharing manner.

Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.

Abstract: A multiple disc clutch apparatus in which driven plates and drive plates are arranged alternately to overlap with each other and which is arranged to be engaged or released in response to an action mode or a non-action mode switched over by the pressing force of a piston, comprises piston regulation means which regulates an amount of movement of the piston so that metallic plates forming the substrates of the driven plates and the drive plates do not adhere to each other.

Abstract: A zoom lens having an optical element for deflecting an optical path includes, in order from an object: a first lens group having positive refractive power; a second lens group having negative refractive power; a third lens group having positive refractive power; a fourth lens group having positive refractive power; and a fifth lens group having negative refractive power. The third lens group has a plurality of lenses, and the following conditional expressions 1.00<PL/fW<1.75 and 0.30<PL/fT<0.45 are satisfied, where PL denotes an optical path length of the optical element for deflecting the optical path, fW denotes a focal length of the zoom lens in a wide angle end state, and fT denotes a focal length of the zoom lens in a telephoto end state.

Abstract: A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145° C. or higher. The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40 at % or more and 65 at % or less in Zn-Ge-Te.

Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.

Abstract: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.

Abstract: A graphical user interface centralizes Level I quote information in the center of a circular display while Level II (or regional) data appears in peripheral bands layered on the outside of the Level I information. The interface is also split into two main sections, a “bid” quote information section and an “ask” quote information section. The bid quote information appears on the left of the interface while the ask quote information appears on the right side of the interface. Through clicking in any one of the peripheral bands, an order can be placed at that price point.

Abstract: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.