Abstract: The invention relates to a condom (10) for the penis. The condom (10) comprises a flexible condom wall (12). In the condom wall plane a shaft channel (18) is arranged in which a flexible rotary shaft (16) is supported. The rotary shaft (16) is adapted to be driven by a rotary drive. The rotating shaft (16) generates stimulating vibrations.

Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.

Abstract: In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

Abstract: A magnetic storage device comprises an array of magnetic memory cells (50). Each cell (50) has, in electrical series connection, a magnetic tunnel junction (MTJ) (30) and a Zener diode (40). The MTJ (30) comprises, in sequence, a fixed ferromagnetic layer (FMF) (32), a non-magnetic spacer layer (33), a tunnel barrier layer (34), a further spacer layer (35), and a soft ferromagnetic layer (FMS) (36) that can change the orientation of its magnetic moment. The material type and thickness of each layer in the MTJ (30) is selected so that the cell (50) can be written by applying a voltage across the cell, which sets the orientation of the magnetic moments of the FMF (32) and FMS (36) relative to one another. The switching is effected by means of an induced exchange interaction between the FMS and FMF mediated by the tunneling of spin-polarized electrons in the MTJ (30).

Abstract: In the chip with which a plurality of MISFET from which threshold value voltage differs is intermingled, leakage current, such as GIDL current and BTBT current, is suppressed, inhibiting the short channel effect of MISFET. The concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively low threshold value voltage is formed is made lower than the concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively high threshold value voltage is formed. Implantation amount of the impurity at the time of forming n? type semiconductor region 19 and punch-through stopper layer 20 in region ALTN is made larger than the implantation amount of the impurity at the time of forming n? type semiconductor region 16 and punch-through stopper layer 17 in region AHTN, respectively.

Abstract: An IC body is loaded to a case 2 made of thermosetting resin material and sealed with a sealing portion made of thermosetting resin material to be integrated, whereby an IC card is manufactured. The IC body comprises: a wiring substrate formed with an external connection terminal at a back surface thereof; a semiconductor chip loaded over a surface of the wiring substrate and electrically connected to the external connection terminal via a interconnect; and the sealing portion made of thermosetting resin material so as to cover the semiconductor chip and a bonding wire. The sealing portion is formed so that the external connection terminal is exposed. The present invention makes it possible to heighten the strength of IC cards and at the same time, to reduce the manufacturing cost and improve the reliability.

Abstract: The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.

Abstract: A stapler comprises a stapling unit and a base movably connected to each other. The base comprises an anvil, a lower and an upper part with a contact surface which has a staple opening against which a workpiece is placed. The upper and lower parts are movably connected to each other. In operation, movement of the stapling unit and the base toward each other drives a staple into the workpiece, wherein the staple crown comes in contact with the workpiece and the staple legs extend through the staple opening. Upon movement of the upper part and stapling unit toward the lower part, the staple legs are bent by the anvil into contact with the underside of the workpiece. The anvil is attached to the base by an elastic element between the lower and upper part, and is urged toward the staple opening to block the opening when the stapler is in an initial position.

Abstract: A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.

Abstract: A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. A memory system including a non-volatile memory (CHIP1), DRAM (CHIP3), a control circuit (CHIP2) and an information processing device (CHIP4) is configured. Data in FLASH is transferred to SRAM or DRAM in advance to speed up. Data transfer between the non-volatile memory (FLASH) and DRAM (CHIP3) can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.

Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.

Abstract: To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7A, 7B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7A, 7B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma enhanced CVD process so that the gate electrodes 7A, 7B are not directly contacted to the silicon nitride film 19.

Abstract: The present invention is a diffractive optical element 1 in which mutually different materials make contact with one another via the same diffraction grating groove 30. One of the mutually different materials is a first ultraviolet curing resin 10 and the other of the mutually different materials is a second ultraviolet curing resin 20 that is different from the first ultraviolet curing resin 10.

Abstract: Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.

Abstract: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

Abstract: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

Abstract: The present invention provides a technology which can suppress a variation in a value after a write operation to minimum so as to facilitate multi-bit operation in a semiconductor device such as a phase change memory. A semiconductor device includes: a memory cell having a storage element (phase change material) that stores information depending on a state change by temperature; an I/O circuit; and means which, when writing data, performs a set operation and an operation for writing desired data, measures a resistance value of the storage element by means of a verify operation, and when the resistance value is not within a target range, performs the set operation and the write operation again while changing a voltage to be applied to the storage element.