Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

Abstract: A method for delivering therapeutic radiation to a tumor within a patient including: monitoring tumor motion in a preliminary procedure to generate and record a surrogate signal representing the tumor motion; determining a radiation therapy plan for the patient including a planned sequence of varying parameters of a radiation beam to track the tumor motion and a planned rate of execution of the planned sequence; configuring a radiation therapy device to deliver radiation in accordance with the radiation therapy plan, positioning the patient within the device, and activating the device to perform the planned sequence; monitoring tumor motion during the procedure to provide a treatment surrogate signal; determining the difference between the estimated and treatment surrogate signals; and regulating the speed of the radiation treatment procedure by varying the rate of execution of the sequence of beam parameters in accordance with the difference between the estimated and treatment surrogate signals.

Abstract: A transmitter circuit has two mixers that modulate a carrier wave according to an input signal, outputs a signal having information in a phase and an amplitude, detects a DC offset in each of the mixers, and adds a DC voltage that corrects the detected DC offset to the input signal of the mixers. The mixer is a double balanced mixer having two load resistors, and the transmitter circuit has a resistor that is connected between a node of two load resistors and a power supply, a limiter amplifier that amplifies a signal, and a control unit that changes first and second potentials using a signal that is outputted by the limiter amplifier. The first and second potentials become a potential of the DC voltage that corrects the DC offset.

Abstract: A plasma processing apparatus which stably and continuously generates a uniform plasma to process large-diameter wafers using a wide range of seed gases under wide-ranging pressure and density conditions and can be thus used for a wide range of applications, ensuring a high production efficiency. The plasma processing apparatus, which introduces electromagnetic waves through a dielectric window into a reduced pressure vessel, has at least two antenna elements which are rotationally symmetrical. One end of each antenna is grounded and power is fed from a high frequency power supply to the other end in the same or virtually same phase.

Abstract: A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.

Abstract: A digital forensic search tool which enables a first entity, such as a federal investigation agency, to share its suspect and sensitive data with a second entity, such as another investigative agency, in a manner that allows the second agency to utilize the suspect data while not revealing the actual content of the sensitive data to the second agency. The second agency can perform comparisons and other operations on the sensitive data without having to know the actual content of the data. The search tool allows an investigative agency to define an investigative strategy for a particular case via the search markup language programs and by the data features that it includes in the search tool. Thus, by sharing search tools among agencies, an agency can share or inform others of that agency's theory of the case and investigative goal.

Abstract: A space conditioning system for a building including production and occupied spaces provides precise control of exhaust and space conditioning equipment by taking into account multiple conditions and by using predictive control. The control method and system are illustrated by a commercial kitchen ventilation application.

Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.

Abstract: A method for secure loading of a key dedicated to securing a predetermined operation into memory of a microchip of an embedded system includes, as a first step, authenticating a security device by generating a first random number using the microchip, transmitting the first random number to the security device, generating a second random number in the security device, generating a first cryptogram from the first and second random numbers by applying an asymmetric signature algorithm using an asymmetric secret key, transmitting at least the first cryptogram to the microchip, and authenticating the security device by verifying the first cryptogram using the public key.

Abstract: Providing a compact lightweight stereomicroscope securing a light weight necessary for carrying, capable of securing stability upon attaching a camera. The stereomicroscope includes a base 1 that places a sample thereon, a microscope body 9 having a pair of left and right observation optical systems for observing the sample and a photographing optical system that leads the light from the sample substantially corresponding to the focusing center of the observation optical systems to a imaging means 17, a column 3 that is disposed on the base 1 and supports the microscope body 9, a support means that supports the imaging means 17, and a connecting means 13 that rotatably connects the microscope body 9 to the column 3. An optical axis I of the photographing optical system becomes substantially parallel to a rotation axis O of the connecting means.

Abstract: Providing a zoom lens system being inexpensive, compact and lightweight with high optical performance, and an imaging apparatus, and a method for varying a focal length. The zoom lens system includes, in order from an object, a first lens group having negative refractive power, a second lens group having positive refractive power, a third lens group having negative refractive power, and a fourth lens group having positive refractive power. Upon zooming from a wide-angle end state to a telephoto end state, a distance between the first and second lens groups decreases, a distance between the second and third lens groups increases, and a distance between the third and fourth lens groups decreases. The second lens group consists of two positive lenses or less and one negative lens. The fourth lens group consists of two positive lenses or less and one negative lens. Given conditions are satisfied.

Abstract: Providing a zoom lens system having excellently correcting various aberrations with accomplishing to be compact, lightweight, and slim upon being retracted. The system is composed of, in order from an object, a first group having negative refractive power, and a second group having positive refractive power. Upon zooming from a wide-angle end state to a telephoto end state, a distance between the first group and the second group varies. The first group is composed of two lens elements which are, in order from the object, a negative lens having a concave surface facing an image, and a positive lens. The second group consists of three lens elements or less and includes, in order from the object, a positive lens, an aperture stop for defining an f-number, and a negative lens component including a negative lens and disposed to the image side of the aperture stop. Given conditions are satisfied.

Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Abstract: High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

Abstract: A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.

Abstract: In a variable frequency oscillator in a semiconductor device, as the variation of an oscillation frequency caused by the variation of temperature and supply voltage and process variation is large, it is difficult to reduce the conversion ratio of control voltage dependent upon phase noise and the oscillation frequency and therefore, phase noise is large. The variation of the oscillation frequency is suppressed and phase noise is reduced by connecting a voltage-to-current conversion circuit that converts input control voltage to control current of a ring oscillator to the ring oscillator where delay circuits a delay time of which increases and decreases according to the amplitude of input control current are cascade-connected by a plurality of stages in a ring and increasing/decreasing current dependent upon any of temperature, supply voltage and the threshold voltage of a transistor inside the voltage-to-current conversion circuit.