Abstract: A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.

Abstract: A grease filter has a filtering portion configured such that fumes enter a major face thereof and flow through a grease extraction filter therewithin in a direction parallel to the major face. A frame that fits into an opening of a hood defines a box structure that is configured to allow flow from the end (or ends) of the filtering portion where flow exits.

Abstract: The present invention is directed to devices, systems and methods for removing undesirable materials from a sample fluid by contact with a second fluid. The sample fluid flows as a thin layer adjacent to, or between, concurrently flowing layers of the second fluid, without an intervening membrane. In various embodiments, a secondary separator is used to restrict the removal of desirable substances and effect the removal of undesirable substances from blood. The invention is useful in a variety of situations where a sample fluid is to be purified via a diffusion mechanism against an extractor fluid. Moreover, the invention may be used for the removal of components from a sample fluid that vary in size. When blood is the sample fluid, for example, this may include the removal of ‘small’ molecules, ‘middle’ molecules, macromolecules, macromolecular aggregates, and cells, from the blood sample to the extractor fluid.

Abstract: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd? higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

Abstract: Systems and methods handle air and rinsing fluid during fluid processing. The systems and methods eliminate air from a fluid processing system prior to, during, and after use. The systems and methods provide a connector assembly for establishing fluid flow from a fluid source. The connector assembly has discrete first and second passages that prevent communication between the fluid in first passage and the fluid in the second passage. Prior to system use, the connector assembly may be utilized in a priming function to remove residual air from a fluid circuit prior to use. The connector assembly may also be utilized after use to perform a rinse-back function.

Abstract: The capacitance of the capacitor with the constant capacitance is equivalently reduced in the capacitance of a resonant capacitor in a voltage control oscillator to increase the variable amount of the capacitance of the resonant capacitor, and to expand an oscillation frequency range. There are provided a differential negative conductance generator circuit having two resonation nodes for differential output, a differential resonant circuit having a variable capacitance that is controlled by voltage control and an inductance connected in parallel to each other, and a differential negative impedance circuit. A resonant circuit and a negative impedance circuit are connected between the resonation nodes. The capacitor with the constant capacitance that occurs between the resonation nodes is reduced by the negative impedance of the negative impedance circuit.

Abstract: The invention concerns the parameterization of a piece of software comprising parameters to be entered in order for the software to be used. The principle consists of subdividing the set of parameters into subsets, and of simultaneously displaying the subsets (SS1, SS2, SS3), the content of at least one selected subset, and the position within the set of each subset selected.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: The present invention relates to heel stabilizing technology. In one embodiment, when incorporated in footwear or a footwear cover, the heel stabilizing technology includes an adjustable heel tension fastener that is used in conjunction with an upper stabilizing means. Once adjusted, the heel tension fastener provides an upwards tension vertical to the upper stabilizing means.

Abstract: According to the present invention, in a one-way clutch used under an environment where lubricating oil including organic molybdenum exists, at least a part of at least one of a plurality of engaging members constituting the one-way clutch is subjected to surface treatment mainly including an element having no affinity with respect to a molybdenum element.

Abstract: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

Abstract: In accordance with an embodiment of the present invention, a blast-resistant panel may include a layer of a pre-cured elastomeric material having a predetermined thickness, a body portion, and a plurality of flanges, each of the plurality of flanges having a substantially equal width and depending away from a same side and at approximately equivalent right angles to the body portion. The blast-resistant panel may also include a plurality of fastener elements for securing the pre-cured elastomeric material layer to a surface of a structure through the plurality of flanges of pre-cured elastomeric material layer.

Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.

Abstract: Embodiments of the present invention are directed to a stirrer tool that includes a head component having a first body portion and a second body portion connected to the first body portion with a first plurality of projections extending substantially radially out from and substantially perpendicular to a longitudinal axis of a body portion. Head component may also have a second plurality of projections extending in a substantially distal direction away from a distal end of the body portion, and all of the projections may be made of a substantially stiff material that is flexible enough to be bent to fit through an opening in a container that is smaller in diameter than a diameter of the head component and stiff enough to mix viscous products.

Abstract: The invention relates to a method for speeding up the time required to perform a Montgomery product calculation by applying the High-Radix Montgomery method on computing hardware. A loop of operations is performed consisting in repeating successive operations, i.e.: a first addition operation involving the addition of a value of one of several first products, designated ai·b and a value of one variable, designated u, according to a first relationship u:=u+ai·b; and a second addition operation involving the addition of a value of one of several second products, designated m·n, and a value of variable u according to a second relationship u:=u+m·n. At least the first and second addition operations are Carry-Save addition operations in order to speed up the time required to perform an addition.

Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.

Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

Abstract: The present invention relates to an annealing control primer for improving annealing specificity in nucleic acid amplification and its applications to all fields of nucleic acid amplification-involved technology. The present primer comprises (a) a 3?-end portion having a hybridizing nucleotide sequence substantially complementary to a site on a template nucleic acid to hybridize therewith; (b) a 5?-end portion having a pre-selected arbitrary nucleotide sequence; and (c) a regulator portion positioned between said 3?-end portion and said 5?-end portion comprising at least one universal base or non-discriminatory base analog, whereby said regulator portion is capable of regulating an annealing portion of said primer in association with annealing temperature.

Abstract: In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.