Patents Represented by Attorney Miles & Stockbridge P.C.
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Patent number: 7525184Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.Type: GrantFiled: May 30, 2003Date of Patent: April 28, 2009Assignee: Renesas Technology Corp.Inventors: Yoshihiko Shimanuki, Yoshihiro Suzuki, Koji Tsuchiya
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Patent number: 7522896Abstract: A conventional method of controlling the passband of a filter involves an increase in cost for a chip due to a large area of a detection circuit for determining the level of an interference wave. The present invention utilizes a result obtained by detecting the amplitude level of a signal with an automatic gain control circuit to appropriately control the passband of a filter. The amplitude level of all the signals including a desired wave and an interference wave is detected by utilizing the automatic gain control circuit to thereby control the passband of a filter on the basis of the result.Type: GrantFiled: October 18, 2005Date of Patent: April 21, 2009Assignee: Renesas Technology Corp.Inventors: Takashi Oshima, Masaru Kokubo
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Patent number: 7522083Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.Type: GrantFiled: October 23, 2007Date of Patent: April 21, 2009Assignee: Hitachi, Ltd.Inventors: Ryusuke Sahara, Mitsugu Kusunoki, Kazutaka Mori, Hiroshige Kogayu
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Patent number: 7520604Abstract: A pair of multi-purpose eyeglasses has a main frame and an inner frame. The main frame includes a lens holder for holding lenses, a pair of temple arms hingedly assembled with opposite side edges of the lens holder, and side assembling ribs protruding from the side edges of the lens holder. The temple arms extends backward from and being capable of pivoting around the opposite side edges of the lens holder, and each of the side assembling ribs has a side assembling groove formed between the side assembling rib and the lens holder. The inner frame is detachably assembled with the outer frame and has side edges each of which can be inserted in the side assembling groove. A sealing member is attached to an inner surface of the inner frame. The inner frame and the outer frame can be easily assembled with or disassembled from each other according to a user's intention.Type: GrantFiled: October 21, 2004Date of Patent: April 21, 2009Assignee: KBC America, Inc.Inventor: Woon-Taek Choi
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Patent number: 7519831Abstract: The present invention concerns a cryptographic system (1) with a modular architecture. Memory modules (3, 3?, 3?) make it possible to store information concerning authentication keys, data and commands, including a secure memory module (3?) for containing the keys with integrity checking and an emergency erase function. Various types of algorithm modules (5, 5?, 5?) perform cryptographic functions of the cryptographic system by executing the commands stored in at least one memory module (3, 3?, 3?). External interface modules (4, 4?, 4?) are utilized that make it possible to produce the link between the cryptographic system (1) and external devices, through a standard or proprietary input/output bus. A control unit (6) is responsible for the supervision of the various algorithm modules and the management of the keys, and a central interconnect module (2) assures handling of secure exchanges between blocks.Type: GrantFiled: November 29, 2004Date of Patent: April 14, 2009Assignee: Bull S.A.Inventor: Patrick LeQuere
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Patent number: 7519774Abstract: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory.Type: GrantFiled: May 17, 2005Date of Patent: April 14, 2009Assignee: Renesas Technology Corp.Inventors: Fumie Katsuki, Takanobu Naruse, Chiaki Fujii
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Patent number: 7518112Abstract: A radiation detection circuit having a multi-channel input used for radiation measurement and capable of canceling cross-talk noise generated from a logic circuit for controlling a channel and enabling low noise radiation measurement easily and precisely. The radiation detection circuit also generates an inverted signal for each of input/output signals needed for controlling its logic and cancels a noise charge generated by coupled capacity between a bonding wire (analog input side in IC package) for connecting its output to another radiation detection circuit and a bonding wire of each of input/output signals of the logic control circuit by generating an inverted noise charge with coupled capacity between the inverted signal and its output when in logic controlling, thereby suppressing the cross-talk noise generated by each of its input/output signals.Type: GrantFiled: January 23, 2007Date of Patent: April 14, 2009Assignee: Hitachi, Ltd.Inventors: Takashi Matsumoto, Satoshi Hanazawa, Toshihiko Moriwaki, Masakazu Ishibashi, Naruaki Kiriki
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Patent number: 7519337Abstract: A transmitter employing variable gain amplifiers and operating with both constant and nonconstant envelope modulation systems is contrived to suppress variation in the transmitting power when constant envelope modulation is performed. The transmitter comprises a PM loop, an AM loop, and a variable gain amplifier which is shared by the PM loop and the AM loop and combines phase information that the PM loop outputs and envelope information that the AM loop outputs by gain control. The variable gain amplifier comprises a variable gain amplifier body having a supply voltage terminal and a bias current detection terminal for extracting a bias current corresponding to a gain, wherein the gain changes with a change in the potential of the supply voltage terminal, and a bias control block connected to the supply voltage terminal and the bias current detection terminal.Type: GrantFiled: December 16, 2005Date of Patent: April 14, 2009Assignee: Renesas Technology Corp.Inventors: Masahiro Ito, Taizo Yamawaki, Yoshiaki Harasawa
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Patent number: 7516903Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secret codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot.Type: GrantFiled: April 7, 2006Date of Patent: April 14, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
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Patent number: 7518790Abstract: Providing a microscope capable of movably adjusting an observation field of a sample without moving the sample. The microscope includes a first objective lens, a second objective lens, a mirror, an angular adjustment mechanism, and a shift mechanism. The first objective lens is disposed to the sample side. The second objective lens forms an intermediate image of the sample together with the first objective lens. The mirror is disposed with a tilt on an optical path between the first objective lens and the second objective lens. The angular adjustment mechanism rotatably adjust the mirror in the tilt direction. The shift mechanism makes a shift adjustment of the second objective lens in an axial direction of a rotation axis of the mirror. With the configuration, the observation field can be moved two-dimensionally by the angular adjustment mechanism.Type: GrantFiled: September 21, 2006Date of Patent: April 14, 2009Assignee: Nikon CorporationInventors: Ichiro Sase, Shuji Toyoda
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Patent number: 7518208Abstract: A semiconductor device has a first region and a second region formed on a surface of a substrate. Plural first conductors and second conductors are formed in the first and second regions respectively. A first semiconductor region and a second semiconductor region are formed between adjacent first conductors. The second semiconductor region is in the first semiconductor region and has a conductivity type opposite to that of the first semiconductor. A third semiconductor region is formed between adjacent second conductors. The third semiconductor region has the same conductivity type as the second semiconductor region and is lower in density than the second semiconductor region. The third semiconductor region has a metal contact region for contact with a metal, which is electrically connected to the second semiconductor region. A center-to-center distance between adjacent first conductors is smaller than that between adjacent second conductors.Type: GrantFiled: July 10, 2006Date of Patent: April 14, 2009Assignee: Renesas Technology Corp.Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
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Patent number: 7515450Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.Type: GrantFiled: May 21, 2007Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Nakajima, Keiichi Yoshida
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Patent number: 7515879Abstract: An RF circuit module, in which a power amplifier and a transceiver are united, with reduced interference between its electronic circuit blocks, downsized and still having high performance, and with a stable performance not dependent on the ground land structure on the motherboard, is provided. The ground plane 110 for at least a last-stage amplifier 11 of the power amplifier 10 where the greatest power is generated in the whole RF circuit block, that is, the source of generating the greatest noise and heat for the RF circuit block, is isolated from the ground plane for at least one circuit portion of the transceiver 9 including an LNA 51, receiver 52, transmitter 30, and VCO 70. These ground planes are connected to a common ground plane 480 through different connection conductors, respectively.Type: GrantFiled: December 17, 2004Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Hiroshi Okabe, Hidetoshi Matsumoto
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Patent number: 7515352Abstract: Providing an ultra-compact zoom lens system having a vibration reduction function, suitable for a compact optical device using a solid-state imaging device. The system includes, in order from an object, a first lens group having positive power and a bending member for bending the optical path by about 90°, a second lens group having negative power, a third lens group having positive power, and a fourth lens group having positive power. Upon zooming from a wide-angle end state to a telephoto end state, the first and third lens groups are fixed with respect to an image plane, the second lens group is moved to the image, and the fourth lens group is moved at first to the object and then to the image plane. An image blur on the image plane caused by a camera shake is corrected by moving the third lens group perpendicularly to the optical axis.Type: GrantFiled: February 5, 2007Date of Patent: April 7, 2009Assignee: Nikon CorporationInventor: Daisaku Arai
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Patent number: 7514908Abstract: The present invention provides a switching power source and a semiconductor integrated circuit which realize an acquisition a sufficient driving voltage of a high-potential side switching element M1 even when a power source voltage VDD is low.Type: GrantFiled: January 14, 2005Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Kyoichi Hosokawa, Ryotaro Kudo, Toshio Nagasawa, Koji Tateno
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Patent number: 7515648Abstract: A transmitter that can reduce noise without using an SAW filter whose IC integration is hard, and copes with two modulation formats of constant envelope modulation and non-constant envelope modulation, and a downsized and low-cost wireless communication apparatus that uses the transmitter are provided. The transmitter includes a quadrature modulator that modulates an input signal by quadrature modulation, a first amplifier that amplifies a modulation signal outputted by the quadrature modulator, and a second amplifier that amplifies an output signal of the first amplifier. The first amplifier operates as a limiter when the modulation format is the constant envelope modulation, and performs linear operation when the modulation format is the non-constant envelope modulation.Type: GrantFiled: December 21, 2004Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Taizo Yamawaki, Masahiro Ito, Masumi Kasahara, Hiroaki Matsui
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Patent number: 7514749Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.Type: GrantFiled: May 18, 2008Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Kunihiko Kato, Masami Koketsu, Shigeya Toyokawa, Keiichi Yoshizumi, Hideki Yasuoka, Yasuhiro Takeda
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Patent number: 7512007Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.Type: GrantFiled: January 9, 2008Date of Patent: March 31, 2009Assignee: Renesas Technology Corp.Inventors: Masaaki Terasawa, Yoshiki Kawajiri, Takanori Yamazoe
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Patent number: 7511897Abstract: A projector optical system for forming a real image by projecting an image of a display element is constituted by, sequentially from a projection side, an aperture diaphragm; and a first lens group having positive refractive power and having, in the interior thereof or on a lens surface at a projection side or at a display element side, a diffraction optical surface formed by a multilayer-type diffractive optical element in which diffraction gratings formed on two diffractive element components are arranged facing each other. The projector optical system is configured so as to satisfy the following expression 0.1<K/L<1.5 wherein L is a total length on an optical axis, and K is a distance on the optical axis from the aperture diaphragm to a surface of the first lens group that is closest to the projection side, and satisfy also the following expression 0.01<?Nd<0.45 wherein ?Nd is a difference between refractive indices of the two diffractive element components for a main wavelength (d-line).Type: GrantFiled: July 16, 2007Date of Patent: March 31, 2009Assignee: Nikon CorporationInventor: Kenzaburo Suzuki
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Patent number: D589797Type: GrantFiled: August 26, 2008Date of Patent: April 7, 2009Assignee: CROWN Packaging Technology Inc.Inventor: Iain Charles Edward Stuart