Abstract: A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.

Abstract: An integrated self-powered and switching electronic circuit regulates a stable reference voltage and comprises a band-gap voltage generator to produce said stable reference voltage for a system circuit block that is generally supplied by the output of the band-gap generator through a comparator and an error amplifier. A regulating loop is provided between the output of the system block and the input of the voltage generator circuit to supply a voltage signal produced by the output of the system block. Advantageously, the voltage generator circuit incorporates both the comparator and the error amplifier.

Abstract: Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

Abstract: A method and apparatus for determining the range of an object. A first image of at least a portion of the object viewed from a first position is generated. A second image of the portion viewed from a second position spaced apart from the first position is generated by calculation from the first image and the distance between the first and second position. It is assumed that all of the portion represented by the first image lies on a radius less than the distance to the object. A third image of the portion viewed from the second position is generated and the range determined by comparison of the first and third images.

Abstract: A microactuator is attached to a first face of a coupling formed on a suspension, so that an R/W transducer projects from an opposite face. A hole in the coupling permits passage of an adhesive mass interposed between a rotor of the microactuator and the R/W transducer. A strip of adhesive material extends between a die accommodating the microactuator and the coupling, and externally surrounds the microactuator. The coupling acts as a protective shield for the microactuator, both mechanically and electrically. The coupling covers the microactuator at the front, and prevents foreign particles from blocking the microactuator. In addition, the coupling electrically insulates the R/W transducer, which is sensitive to magnetic fields, from regions of the microactuator biased to a high voltage. With the coupling, the strip forms a sealing structure, which in practice surrounds the microactuator on all sides.

Abstract: A digital decimation filter includes a set of cascaded integrator stages for generating a first signal comprised of bit words including a first number of bits as well as a set of cascaded derivative stages for receiving said first signal and generating therefrom an output comprised of bit words including a second number of bits. The second number of bits is smaller than said first number of bits and a bit discarding unit is located downstream of the integrator stages and upstream of the derivative stages for discarding a given number of least significant bits from the bit words of the first signal before this is received by the derivative stages. Said given number is defined as the difference between said first and said second number of bits.

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

Abstract: A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.

Abstract: The present invention refers to a fully differential operational amplifier of the folded cascode type. In one embodiment the fully differential operational amplifier comprises: a differential input stage able to drive a differential output stage; said differential output stage includes a first branch having at least a first and a second transistor, and a second branch having at least a third and a fourth transistor; said first and second branch are coupled to a first and a second voltage source; a feedback circuit of said first, second, third and fourth transistors that is constituted by a single amplifier having four inputs and four outputs, said four inputs taking the voltages present on a terminal of said first, second, third and fourth transistors, and providing voltages to the control elements of said first, second, third and fourth transistors, which voltages depend on the input voltages of said four inputs.

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device includes a power region, itself having at least one P/N junction provided therein which comprises a first semiconductor region with a first type of conductivity extending into the substrate from the top surface of the device and being diffused into a second semiconductor region with the opposite conductivity from the first; and an edge protection structure of substantial thickness and limited planar size incorporating at least one trench filled with dielectric material.

Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.

Abstract: A noise compensating device in a discrete time control system, such as a R/W system for hard disks, including: a control loop generating a first timing signal, a signal indicative of a quantity to be controlled, and a control signal, which have a first frequency; and an open loop control line which generates a compensation signal synchronous with the control signal and includes a sensor. The sensor includes a sensing element, generating an analog signal, an acquisition stage, connected to the sensing element and generating a disturbance measure signal correlated to the analog signal and synchronous with the control signal, and a synchronization stage. The synchronization stage includes a frequency generator having an input receiving the first timing signal and a first and a second output connected to the acquisition stage and generating, respectively, a second timing signal and a third timing signal.

Abstract: A microelectromechanical structure, usable in an optical switch for directing a light beam towards one of two light guide elements, including: a mirror element, rotatably movable; an actuator, which can translate; and a motion conversion assembly, arranged between the mirror element and the actuator. The motion conversion assembly includes a projection integral with the mirror element and elastic engagement elements integral with the actuator and elastically loaded towards the projection. The elastic engagement elements are formed by metal plates fixed to the actuator at one of their ends and engaging the projection with an abutting edge countershaped with respect to the projection.

Abstract: A method of identifying fingerprints, the method including the steps of acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.

Abstract: The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step; a comparator connected to the output of the input stage, receiving a boosted voltage, and generating a first control signal, the state whereof depends upon the comparison of the voltages at the inputs of the comparator; a logic circuit connected to the output of the comparator and generating a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal; and a switching circuit controlled by the first control signal, by the second control signal, and by the third-level signal and supplying each time the highest among the supply voltage, the boosted voltage, and the programming voltage.

Abstract: The voltage converter circuit has first and second input terminals, and first and second output nodes, and comprises: a first power switch connected between the first input terminal and the first output node; a second power switch connected between the first output node and the second input terminal; a first delay circuit having first and second terminals connected between the first input terminal and a control terminal of the first power switch; and a second delay circuit having first and second terminals connected between the first output terminal and a control terminal of the second power switch. Each delay circuit detects a variation in the voltage supplied on the respective first terminal and detects an operating condition of the respective power switch on the second terminal, and supplies to the control terminal of the respective power switch a switching on delay signal.

Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: The invention includes a multichip integrated circuit package having at least two chips electrically isolated from one another. Within the multichip integrated circuit package is a slug that is directly coupled to at least two chips, without any intervening insulating layers. The slug is physically separated at an appropriate place between the two chips, so that electrical interference between the two chips is effectively eliminated. Making the integrated circuit package begins with directly attaching the two chips to a heat dissipating slug. The heat dissipating slug can have a pre-cut groove running between the chips. Once the chips are attached to the slug, the slug is molded into the multichip integrated circuit package. Then, the slug is physically separated into two pieces from the underside, the separation running along the pre-cut groove. Usually the slug would be separated by being cut by a saw.