Abstract: A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract: A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer.

Abstract: Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

Abstract: Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

Abstract: A process for forming a silicon oxide-filled shallow trench on the active surface of a silicon chip starts with forming a trench in the silicon chip that has an upper portion with vertical side walls and a lower portion with tapered side walls. Then oxygen is implanted selectively into the walls of the lower portion of the trench and the chip is heated to react the implanted oxygen with the silicon to form silicon oxide. The rest of the trench is then filled with deposited silicon oxide, typically by depositing a layer of silicon oxide over the surface and then planarizing the deposited silicon oxide essentially to the level of the top of the trench. The silicon-filled shallow trench serves to divide the surface portion of the chip into discrete regions, each for housing one or more circuit components of an integrated circuit.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the PNP transistor.

Abstract: A fluid delivery system (10, 210) is disclosed that includes a pipeline network (20, 220) having a chemical supply line (12, 14, 212), a filtering system (134, 235), a feeding portion (24, 224), and a return portion (26, 226). A first tank (28, 228), a second tank (30, 230), and a third tank (32, 232) are coupled to the feeding portion (24, 224) and the return portion (26, 226) of the pipe network (20, 220). A control module (100) is coupled to a multiplicity of valves (46, 52, 48, 54, 50, 56, 70, 86, 72, 88, 74, 90) for controlling the flow of the fluid through the system in a manner that provides a continuous and bumpless flow of the fluid. Additionally, the system (10, 210) may include a plurality of sensors (94, 96, 98) that allow control module 100 to sense the volume of fluid in the system (10, 210) and each tank (28, 30, 32, 228, 230, 232).

Abstract: Methods are provided for cleansing contaminants from substrates, such as semiconductor wafer handling implements, and thereby reduce the incidence of contamination of semiconductor devices being assembled upon the semiconductor wafers. In one aspect of the invention, a substrate such as a semiconductor cassette or other semiconductor wafer handling implement, is inserted into a chamber that is substantially isolated from a surrounding environment. A pressurized, and optionally purified, cleansing medium is directed against at least one surface of the substrate to dislodge contaminants from the substrate surface. Dislodged contaminants are evacuated with negative pressure from the chamber. In a preferred aspect of the invention, the cleansing medium is an inert gas, such as nitrogen, and is applied to the substrate at a pressure from about 10 p.s.i. to about 100 or more p.s.i.

Abstract: The invention is to a semiconductor package and the method of making the package. A moisture resistant coating such as a ceramic material is applied over a plastic packaged semiconductor device to seal the package from moisture.

Abstract: An apparatus for use in a removable tab procedure whereby tabs (7) are affixed to the pads (3) by initially having the bonding surface as flat as possible so that bonding pressures from pad to pad are relatively uniform. Bonding is preformed with the pressure applied to the pads being such that the tabs can later be easily removed without damage to the die pads, yet sufficiently strong so that the tabs do not come loose during burn in and testing. A bond strength pull between about 5 and about 40 grams per pad is appropriate for this purpose. The tabs are removed by placing the tested die (1) and attached tabs in a fixture (11) and providing a tool (31) dimensioned and moved along a path (13, 15, 17, 19) whereby each of the tabs is serially removed with the pressure applied to each tab to provide removal being preferably no greater than 40 grams.

Abstract: The present invention provides a thermally enhanced molded cavity package (10) having a package body (12) with upper (40) and lower (42) sections. The package body (12) has a cavity (22) with the cavity opening (32) in the upper section (40) of the package body (12). The present package (10) includes a lead frame (14) with a plurality of individual leads (16) that are external to the cavity (22) and a plurality of lead fingers (28) that are internal to the cavity (22). The present package (10) also includes a heat spreader (34) for increasing heat dissipation from the package (10) in the lower section (42) of the package body (12) and coupled to the lead frame (14). The heat spreader (34) has a first surface (26) forming a floor of the cavity upon which a microcircuit chip (24) may be mounted and a second surface forming a base (36) of the package body (12).

Abstract: A memory array architecture is disclosed which funnels data through a series of sets of input/output data lines. Additionally, the invention allows a variable number of sense amplifiers to be used with a single local differential amplifier, thereby permitting high speed sensing.

Abstract: A display system for non-destructive inspection of integrated circuit packages is disclosed for producing acoustical reflected images from selected planes within an integrated circuit package to detect flaws within the package.

Abstract: A titanium nitride layer is deposited between the metal titanium layer and the oxide cap of a conventional oxide capped titanium disilicide technology process. This titanium nitride layer is deposited in-situ after a certain thickness of metal titanium has been deposited by bleeding nitrogen gas into the titanium sputter machine. Thereafter the normal oxide cap is deposited over this titanium nitride layer. The normal titanium react process is performed to produce titanium disilicide. After the titanium disilicide has been produced, it is then necessary to strip off the oxide cap. The extra titanium nitride layer makes it is possible to use a wet etch to remove the oxide cap, with the titanium nitride layer serving as a etch stop. In this manner an isotropic wet etch may be employed to remove all of the oxide cap layer. The isotropic wet etch is preferably a 10% buffered HF etch.

Abstract: Hierarchical multiprocessors systems with common level expansion modules. The invention includes an architecture for such multiprocessor system.

Abstract: A CMOS on chip mid-rail voltage generation circuit is provided for an analog ground reference. A voltage divider establishes a current path between the high and low rail, and supplies a mid-level voltage to one input of a differential amplifier. A pair of series connected field effect transistors are also connected between the high and low voltage rails, with their common connection providing the input to the other input of the differential amplifier. A pair of open loop output transistors are also coupled in series between the high and low voltage rails, and each has their gate coupled to one of the series connected pair, and is also matched to that pair.

Abstract: The invention is to a semiconductor package and the method of making the package. A moisture resistant coating such as a ceramic, silica or other plastic material is applied over a plastic packaged semiconductor device to seal the package from moisture.

Abstract: A source side injection non-volatile memory cell is provided that comprises a floating gate and control gate stack (12) disposed outwardly from a channel region (26) formed on an (n-)-substrate (10). Drain region (32) and source region (30) are formed on opposite sides of stack structure (12). Source side injection of hot electrons occurs between source region (30) and floating gate (18) when relatively low voltages are placed on gate conductor (22).

Abstract: A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.

Abstract: An address match scheme is disclosed which allows the alternate selection of fuses blown based on either logic ones or logic zeros in an address.