Abstract: An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises I.sub.DDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for I.sub.DDQ test purposes only.

Abstract: An electronic circuit includes an array of a number of memory cells that are functionally organized in rows and columns. The circuit includes test circuitry that is selectively operative to access all cells of the array in parallel. An I.sub.DDQ -test then discovers whether or not there is a defect in any of the cells. This results in a test circuit which is faster, more efficient and more economical than previously-available circuits.

Abstract: An insulated gate field effect device (1a,1b,1c,1d) has a semiconductor body (2) with a first region (3) of one conductivity type, a second region (4) of the opposite conductivity type, a third region (6) of the one conductivity type (7) separated from the first region (3) by the second region (4) and at least one injector region (8) for injecting charge carriers of the opposite conductivity type into the first region (3). The conduction channel area (40) adjoining the insulated gate (9, 10) has first and second subsidiary areas (40 and 40b) for providing respective first and second subsidiary conduction channels.

Abstract: An integrated device combines a bipolar transistor (10) and a junction field effect transistor (12) so as to produce an output voltage (Vd) which is higher than the breakdown voltage (BV.sub.CEO) of the bipolar transistor (10). A lateral extension (30) of the base zone (28), which forms a gate, is provided with an opening (38) in which a drain region (40) of the field effect transistor is situated. A heavily doped peripheral region (36) of the same type as the drain region (40) surrounds the lateral extension (30) on three sides, while a heavily doped buried layer region (34), which forms a conductive part of the collector of the bipolar transistor (10), extends to below the peripheral region (36) and forms with the latter the source of the field effect transistor (12). The resulting device has substantially improved breakdown voltage characteristics.

Abstract: A high frequency amplifier circuit using hybrid nested Miller compensation (HNMC) as a means to frequency compensate amplifiers. The circuit comprises four amplifier stages, or any other even number higher than four. Each of the four stages can be inverting or balanced pair stages. The Miller compensation is provided by capacitors connected across the output and input of several of the stages, and with a third capacitor connected across the other stages. The HNMC circuit allows the use of lower supply voltages, consumes less supply power, and avoids the need to drive the output transistor with a differential stage. Other variations employ a multipath input stage, and opamps comprising 6 and 8 stages are also described.

Abstract: A high-voltage differential sensor includes an attenuator formed of two matched monolithic capacitance divider networks. Each divider network is formed of a series connection of monolithically integrated capacitors, which together generate an attenuated differential signal from a high-voltage differential input signal. The attenuated differential signal from the capacitance divider networks is then amplified and fed to a comparator, which generates a first output level when the high-voltage differential input signal is above a selected level, and generates a second output level when the high-voltage differential input signal is below the selected level. By using monolithically integrated capacitors in the divider networks of the attenuator, a simple, compact, low power, high performance high-voltage differential sensor is obtained.

Abstract: A semiconductor device including a vertical transistor, for example of the pnp type, having a p-type substrate (1) which forms the collector, with at its surface an epitaxial n-type layer (3) in which a p-type emitter region (15, 16) is formed, while the portion (9) of the epitaxial layer (3) lying between the emitter (15, 16) and the collector (1) forms the base. In this vertical transistor, the current gain is very strongly increased when the emitter is formed by a first partial emitter region which is weakly p-type doped and which extends below an insulating layer (6) and by a second partial emitter region (16) which is strongly p.sup.++ -type doped and which extends below the contact zone (26) of the emitter defined by an opening in the insulating layer (6). The respective thicknesses and doping levels of the first (15) and second (16) emitter regions are provided such that the first region is transparent to electrons and the second forms a screen against electrons.

Abstract: A method of manufacturing semiconductor devices with a passivated semiconductor body (1) provided with an electrode (2) and fastened on an electrically conducting support body (3), in which method a slice of semiconductor material (5) is fastened on a surface (6) of an electrically conducting auxiliary slice (7), and mesa structures (8) are formed in the slice of semiconductor material (5) by the application of grooves (9) in the slice of semiconductor material (5) subsequently, a layer of insulating material (10) is provided on the walls of the grooves (9), electrodes (2) are provided on upper sides (11) of the mesa structures (8), and the auxiliary slice (7) with the mesa structures (8) is split up at the areas of the grooves (9) into individual semiconductor bodies (1) each fastened on its own support body (3).

Abstract: The invention relates to an integrated circuit, having an output stage with at least two respective output transistors, respective main current channels of which are connected in parallel between a first supply terminal and the output. A control circuit ensures that, in response to a variation in an input signal on the input, the charging of respective control electrodes of the at least two respective output transistors commences with a delay relative to one another. The peak value of the time derivative of a current output together by the at least two output transistors is thus limited. After the start of charging, a speed of charging of the control electrode of at least one of the two respective output transistors is reduced. The peak value of the time derivative of the current applied to the output by the at least one of the at least two output transistors is thus reduced.

Abstract: A digital phase-locked loop includes a digital controller whose output is coupled to a controllable oscillator and which loop comprises a phase detector (PD) whose two inputs are provided to receive a pulse-shaped reference signal (REF) and a pulse-shaped oscillator signal (OSC) generated by the oscillator. This phase detector comprises a first circuit branch provided to receive the reference and the oscillator signal, to form a pulse-shaped signal whose pulse width is equal to the distance in time between two specific successive pulse edges of the reference and oscillator signal, to filter by low-pass filter the pulse-shaped signal and to code sample values of the low-pass filtered signal with a first number (Nf) of least significant bits.

Abstract: A current divider for linearly dividing a first signal current (Ii10) into a second and a third signal current (Io11, Io12) includes a first terminal (I10) for the passage of the first signal current (Ii10), a second terminal (O11) for the passage of the second signal current (Io11) and for receiving a first potential, a third terminal (O12) for the passage of the third signal current (Io12) and for receiving a second potential, a first MOS transistor (M1) having a control electrode and a main current path, and a second MOS transistor (M2) having a control electrode and a main current path, the control electrodes of the first and the second MOS transistor (M1, M2) being coupled to a first reference terminal (R10) for receiving a first reference voltage (Rv10) to realize a conductive state of the first and the second MOS transistor (M1, M2) during a first active state of the current divider, the main current path of the first MOS transistor (M1 ) being coupled between the first terminal (I10) and the second te

Abstract: A method of manufacturing an optoelectronic semiconductor device includes the step of providing two comparatively thin layers next to one another on a substrate by means of a non-selective growing process, an etching process, and a selective growing process, a cladding layer being present over said thin layers. In the known method, first the one thin layer and the cladding layer are grown, the latter is locally removed, and the other thin layer and the cladding layer are then grown in that position. This method has the disadvantage that unevennesses (steps or openings) often arise at the surface of the layer structure above the transition between the thin layers.

Abstract: A semiconductor device with a semiconductor body (1) includes a surface region (3) of a first conductivity type which adjoins a surface and in which a field effect transistor is provided which includes a channel region (7) with a gate electrode (8) above it, and a source region (4), a drain region (5) and a drain extension region (6). The drain extension region (6) serves to improve the drain breakdown voltage of the field effect transistor. In practice, a high breakdown voltage is accompanied by a comparatively high on-resistance of the transistor. According to the invention, the drain extension region (6) has a geometry different from that in known transistors, i.e.

Abstract: A semiconductor device having a programmable memory cell which includes a bipolar transistor of which a base region (13) can be provided with a base current through a control transistor (7, 8, 9, 10). The bipolar transistor has an emitter region (12) connected to a first supply line (151) and has a collector region (14) connected to a second supply line (152) through a load (16). A constant potential difference is maintained between the two supply lines (151, 152) during operation. The collector region (14) is laterally electrically insulated and provides a feedback to the control transistor in such a manner that, during operation within a certain voltage domain, a change in the voltage difference between the emitter region (12) and the collector region (14) leads to an opposite change in the conductivity through the control transistor.

Abstract: An optoelectronic semiconductor device includes a first cladding layer (1) of the first conductivity type provided on a substrate (11), an active layer (2), a second cladding layer (3) of a second conductivity type, an intermediate layer (4), and a third cladding layer (5) also of the second conductivity type, the thickness of the second cladding layer (3) being such that the intermediate layer (4) lies within the optical field profile of the active layer (2), while the intermediate layer (4) includes a semiconductor material with a lower bandgap than the second (3) and third (5) cladding layers. Such devices, often in the form of diode lasers, are used inter alia in optical glass fibre communication and optical disc systems. A disadvantage of such devices is that their starting currents are comparatively high.

Abstract: A semiconductor body (2) has first and second major surfaces (2c and 2d) with a first region (2b) of one conductivity type adjacent the first major surface (2c). An insulated gate field effect transistor (6) is formed within the first region (2c) and has source and drain electrodes (S and D) and an insulated gate electrode (G). At least one further component (R4) is coupled between the insulated gate electrode (G) of the insulated gate field effect transistor (6) and a gate input terminal (GT). The further region requires a second region (21) of the opposite conductivity type provided within the first region (2b) so that a region (26) of the further component (R4), the second region (21) and the first region (2b) form a parasitic bipolar transistor (B).

Abstract: An electronic circuit comprises a programmable cell that comprises a cell input, an output, a programmable component, programming means for selectively changing a state of the component, and coupling means for providing a signal path from the cell input to the output dependent on the component's state. The programmable component, e.g., a fuse, is located outside the signal path. Capacitances that limit the speed of operation in the read mode are considerably lower than in the prior art.

Abstract: A shift register or other electronic drive circuit, for an LCD or other active matrix device includes a series of circuit blocks each having redundancy in the form of parallel circuit paths. When the circuit is turned on, self-testing and redundancy selection is carried out by individual test and control arrangements which are associated with the circuit blocks. The test and control arrangements may comprise memory elements, such as a bistable, which electrically program themselves in response to their electrical testing of the circuit paths so as to generate a control signal at an output coupled to one or more output switches. The output switches control which of the parallel circuit paths provides an output to the active matrix device. Each test and control arrangement also comprises a routing circuit controlled by the control signal, for transmitting the correct serial output of that circuit to all serial inputs of a next circuit block.

Abstract: A circuit integrated on a semiconductor substrate in order to drive a load, (for example, a VFD) by means of a comparatively high voltage (for example, 35 V), includes a first and a second supply voltage terminal for application of the comparatively high voltage, an input, and a load output for connection of a load to be driven by the circuit. A switching transistor, a protection transistor and a sub-circuit are a part of the integrated circuit. The switching transistor and the protection transistor are connected in series with the gate of the switching transistor connected to the input. The source of the switching transistor is connected to a first supply voltage terminal, and the drain of the protection transistor supplies a signal for the sub-circuit during operation. The output of the sub-circuit is connected to the load output and the gate of the protection transistor receives a fixed voltage. The protection transistor is constructed so that it limits the voltage at the drain of the switching transistor.

Abstract: A bipolar lateral transistor, for example of the pnp type, is contained in a semiconductor device. The lateral transistor has a p-type emitter region and a p-type collector region laterally spaced apart by an n-type base region. This lateral transistor is formed in an n-type epitaxial layer at the surface of a p-type substrate. The transistor further has a n.sup.++ -type buried layer. The current gain in this lateral transistor is strongly increased by forming the emitter from a first partial emitter region which is weakly p-type doped and extends below an insulating layer, and a second partial emitter region which is strongly P.sup.++ -type doped and extends below the contact zone of the emitter, which is defined by an opening in the insulating layer. The respective thicknesses and doping levels of the first and second emitter regions are provided such that the first region is transparent to electrons and the second region forms a screen against electrons.