Abstract: Compact g.sub.m -control circuits for CMOS rail-to-rail input stages operating in strong inversion are provided. The G.sub.m -control circuit makes the sum of the gate-source voltages of the complementary input transistors, and therefore the g.sub.m of the input stage constant. The compact g.sub.m -control circuits implement a floating voltage source in the form of circuit elements between the N and P-channel input stage transistors and the positive and negative supply rails of the operational amplifier.

Abstract: A semiconductor device is provided with an organic material which is formed by a solid-state mixture of organic donor and organic acceptor molecules. A semiconducting solid-state mixture is known with molar ratios between donor and acceptor molecules of 1.3:2 and 1.66:2. The known solid-state mixture has the disadvantage that its electrical conductivity is comparatively high, so that it is not possible to manufacture switchable devices from the mixture. Here the material includes an n- or p-type semiconductor material, the n-type semiconductor material having a molar ratio between the donor and acceptor molecules below 0.05, and the p-type semiconductor material having this ratio above 20. These solid-state mixtures may be used for manufacturing switchable semiconductor devices. The n- and p-type organic solid-state mixtures can be used for manufacturing transistors, diodes, and field effect transistors in a same manner as, for example, doped silicon or germanium.

Abstract: In a transmission system or a recording systems often codes are used to make the coded signal (C.sub.k) DC free. To simplify the detector (16), block codes can be preferable. To exploit the redundancy inherently present in such a code a symbol wise Viterbi detector (24,26) is used to detect the symbols without largely enlarging the complexity of the system.

Abstract: A low-power CMOS driver circuit capable of operating at high frequencies includes a CMOS output driver circuit and a pair of CMOS predriver circuits for driving the CMOS output driver circuit. A timing circuit is provided for generating three different timing signals for switching the predriver circuits in such a manner that the CMOS driver circuit is capable of operating at frequencies above 1 MHz without dissipating significant power.

Abstract: In the manufacture of a large-area electronic device (e.g. an active-matrix liquid-crystal display or other flat panel display), a TFT of improved lifetime stability results from the inclusion of a field-relief region (22) which is of lower doping concentration than the drain region (12) and which is formed in an area (2) of lateral separation between the channel region (21) and the drain region (22). An energy beam (40), e.g. from an excimer laser, is used to provide the field-relief region (22), by laterally diffusing the doping concentration of the drain region (12) along an area (2) of the semiconductor film (20) significantly larger than the thickness of the semiconductor film (20). The method is simple and easily controllable, an advantageous doping profile (FIG. 3b) is obtained along the field-relief region (22) by this lateral diffusion.

Abstract: A new logic family is identified that achieves much better speeds than CML logic gates. This new logic family operates with multiple inputs and a single logic level, using differential pairs of transistors for each input transistor of the multiple input. This new logic family enables high speed operation, or higher speed, than the prior art, together with lower operating current and a power-delay enhancement significantly increased over the prior art.

Abstract: A semiconductor device of the RESURF type with a "low-side" lateral DMOST (LDMOST), comprising a semiconductor body (1) of predominantly a first conductivity type and a surface region (3) adjoining a surface (2) and of a second conductivity type. The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3) with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is present at a distance from the back gate region (5). A separation region (15) of the first conductivity type is provided around the LDMOST in the surface region (3), which separation region adjoins the surface (2) and extends towards the semiconductor body (1).

Abstract: Each imaging element (2a) of an array (2) includes a photosensitive element (3) for sensing light incident on the imaging element (2a) and for storing charge representing the incident light and a rectifying element (D1). The imaging elements (2a) are arranged in rows and columns with each photosensitive element (3) and the associated rectifying element (D1) being coupled in series between an associated first conductor (4) and an associated second conductor (5, 6) for allowing charge stored at a selected imaging element (2a) to be read out by applying voltages to the second conductors (5, 6) to forward bias the rectifying element (D1) of the selected imaging element to cause a current representing the charge stored at the photosensitive element (3) of the selected imaging (2a) element to flow through the associated first conductor (4).

Abstract: A comparator has a simple high frequency signal path from input to output formed by two differentially connected transistors with an output transistor connected to each. A current control circuit maintains a constant total current flowing through the differentially connected transistors. The ratio of currents flowing through the differentially connected transistors is initially set by a control circuit, so that the output of the comparator is predictable when powered up. The control circuit then gradually releases control, so that there is a smooth transfer to control by a reference signal input to the comparator.

Abstract: An electrically erasable and programmable read only memory (EEPROM) is provided with an insulated control gate and an insulating floating gate in a trench in a semiconductor body. A dielectric layer is disposed along the sidewalls of the trench to separate the floating gate and the semiconductor body. The thickness of the dielectric layer along at least one sidewall of the trench is greater than the thickness of the dielectric layer along the other sidewalls of the trench in order to increase the programming speed due to a higher electric field in the gate oxide along the remaining sidewalls.

Abstract: A two-line multi-station bus system has a clock wire and a data wire and supports selective slave station addressing by a prevalent master station for thereupon eliciting a bitwise clocked data transfer between the clocking master station and an addressed and clocked slave station. Moreover, the system supports analog signal transfer in that the prevalent master station has a holding member for while eliciting the analog signal from the actual addressed slave station holding said clocking through carrying the clock wire at a predetermined binary value. The analog signal is received until changeover of the clock wire to a binary value other than the predetermined binary value a particular version the analog signal is pulse width modulated in combination with associate delimiting signals on the clock wire sent by the transmitter station that is not necessarily the master station.

Abstract: An image detector (1, 1a) has an array (2) of sensors (3) formed from layers of material provided on a substrate (4) and separated from a biasing electrode (5) by a radiation conversion layer (6) in which charge carriers are generated in response to incident radiation. Each sensor has a collecting electrode (7a, 7b) for collecting charge carriers generated in the radiation conversion layer (6), a capacitor (c) for storing charge and a switching element (8) having at least first and second electrodes (9 and 10) with one (10) of the first and second electrodes being coupled to the collecting electrode (7a, 7b) for enabling charge carriers stored at the sensor (3) to be read out.

Abstract: A circuit arrangement includes a wear detector which is proportioned or which operates so that it wears (i.e., fails) faster than the other parts of the circuit arrangement. The wear detector may be made to wear faster than other parts of the circuit by being more heavily loaded during operation, by being configured to be more heavily stressed during operation, or by being subjected to more severe operating conditions. An indicator is connected to the wear detector so that, when the wear detector ceases to function, the indicator signals that the circuit arrangement is near the end of its useful life and is to be replaced.

Abstract: An IF limiting amplifier uses localized positive feedback in each amplifier stage to provide additional small signal gain while maintaining the limiting gain. The extra small signal gain results in higher overall sensitivity for the receiver at less bias current. The reduction in the number of stages needed to perform the same signal response results in a significant decrease in power consumption by the circuit.

Abstract: A method of manufacturing an integrated lateral transistor in which the depth and the doping level of the emitter region are such that the diffusion length of the minority carriers vertically injected into it is larger than or equal to the thickness of the emitter region. The distance between the peripheries of an electrical emitter connection zone and the emitter region is nominally larger than the alignment tolerance of an emitter contact window. This permits obtaining a transistor having an improved current amplification. An integrated circuit includes a lateral transistor, in which the ratio between the surface of the emitter region and that of the electrical emitter connection zone advantageous lies between 20 and 200.

Abstract: An optoelectronic semiconductor device (100) includes a laser (10) which emits a first radiation beam (80) with a first wavelength (.lambda..sub.1) at one side (50) and which forms a radiation waveguide (3) for a second radiation beam (90) with a second wavelength (.lambda..sub.2) greater than the first wavelength (.lambda..sub.1), which second beam can enter the laser (10) at said side (50), and a photodiode (20) present at the other side (60) of the laser (10), aligned with the laser (10), and sensitive to radiation of the second wavelength (.lambda..sub.2).

Abstract: A transformerless high-voltage generator circuit includes an amplifier and a feedback circuit connected together to form an oscillator. Due to the configuration of the feedback circuit, a high-voltage output is obtained at an intermediate point within the feedback circuit without the use of a transformer. The resulting circuit may be used in various applications, such as an electronic photoflash unit, in order to reduce the size, weight and cost of the finished product by eliminating the need for a transformer to obtain the desired high voltage.

Abstract: An integrated circuit, includes an output stage with an input which is coupled to a first and a second gate of an NMOS transistor and a PMOS transistor, respectively, and an output which is connected to a first and a second supply terminal via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor and a switching circuit. The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching circuit is rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.

Abstract: An apparatus and method for improving the speed and accuracy of a feedback amplifier when the primary feedback around the amplifier configuration has been interrupted is provided. An additional feedback loop added to the input stage of the amplifier maintains the circuit response by maintaining the feedback and preventing the saturation of the circuit components.

Abstract: A reference current source for generating a reference current (Irf) includes a bipolar first transistor (2) and a bipolar second transistor (4), the base of the first transistor (2) being coupled to the base of the second transistor (4), a first resistor (6) connected between the emitter of the first transistor (2) and the emitter of the second transistor (4), and a second resistor (8) connected between the emitter of the second transistor (4) and a supply terminal (10).