Abstract: A silicon-on-insulator (SOI) material is formed from a bonded silicon wafer structure which includes, in order, a silicon handler substrate, an insulating oxide layer, a silicon device layer, a highly-doped silicon etch stop layer, and a top silicon substrate. The bonded silicon wafer structure is etched in a first anisotropic etching step to remove the top silicon substrate and expose the etch stop layer. Subsequently, a second anisotropic etching step is performed to remove a major portion but less than all of the etch stop layer, with the second anisotropic etching step continuing only until a substantially maximum degree of thickness uniformity is obtained in a remaining portion of the etch stop layer. The remaining portion of the etch stop layer is then removed, to yield a silicon-on-insulator material having a high degree of thickness uniformity.

Abstract: In charge coupled imaging devices, a major portion of the photosensitive surface area is covered by electrodes with which the charge storage and the charge transport in the semiconductor body are controlled. These electrodes are preferably made of polycrystalline silicon. This material, however, like other conductive materials known per se, has a comparatively high absorption coefficient, in particular in the short-wave portion of the visible spectrum (blue), which adversely affects the sensitivity. According to the invention, the electrodes are manufactured partly from a very thin poly layer, preferably not thicker than 50 nm, and partly from a less transparent but higher conductivity layer, for example, poly of much greater thickness.

Abstract: A semiconductor device is provided having a substrate which includes a floating circuit well with turn on/turn off signals generated by a voltage drop proximate to at least one resistor contained therein, and having high-voltage interconnects to connect the drain terminals of a plurality of LDMOS transistors to the resistor in the floating well and wherein the transistors, resistor and floating well are combined into an integrated structure which eliminates the high voltage interconnect crossovers.

Abstract: An interface circuit for linking microprocessors, intended to limit the current (Iout) in the link (L1-L2) by inserting in the link the emitter-collector path of a first transistor (T.sub.1) which is in the saturated state during operation. This circuit includes a second transistor (T.sub.2) which has a geometry k times smaller than that of the first transistor (T.sub.1) and which is coupled to the first transistor (T.sub.1) so as to produce a copy (Iy) of the link current (Iout), and a base current generator (10) which produces an output current (Iz) which feeds the bases of the first and the second transistor (T.sub.1, T.sub.2), and which is a regressive function of the copy current (Iy), on the basis of a fixed reference current (I.sub.0). A pair of transistors (T.sub.3, T.sub.4), similar to the first and the second transistor (T.sub.1, T.sub.2) but connected to the link (L1-L2) in an inverted manner, provides protection for bidirectional operation.

Abstract: An important problem in large integrated circuits is constituted by noise superimposed on the supply. This noise is particularly caused by switching of switching elements such as flipflops, and by heavily loaded output stages. These elements cause current peaks which may give rise to comparatively great fluctuations in voltage. This problem is solved at least to a great extent in CMOS circuits with standard cells or with custom layout blocks by means of an additional decoupling capacitance in the form of an extra well in the routing channels. The decoupling capacitance may be positioned immediately adjacent the switching element, which is favorable for suppressing the supply noise. Since the routing channels are generally not used for providing circuit elements, the chip surface area is not or substantially not increased by this extra capacitance.

Abstract: A semiconductor body (10) has a first region (13) of one formed a semiconductor device (Rx) having a resistance which varies with temperature. The semiconductor device (Rx) is formed by a second region (14) of the opposite conductivity type formed within the first region (13) and a third region (15) of the one conductivity type formed within the second region (14), with first and second electrodes (16) and (17) being spaced apart on the third region (15) so that a resistive path is provided by the third region (15) between the first and second electrodes (16 and 17) and a reference electrode (18) connecting the second region (14) to a reference potential.

Abstract: It is known to reduce the leakage current or dark current in charge-coupled devices with buried channels such as, for example, charge-coupled imaging devices by bringing the surface to the inverted state. In such a device, however, it is not possible to empty the channel completely locally in usual manner in that the charge is drained off through the substrate by means of a voltage pulse applied to the gates (charge reset). To be able to carry out charge reset nevertheless, the voltage pulse is applied between the substrate and the intermediate zone interposed between the substrate and the CCD channel. Since this voltage pulse is active over the entire range of the device, the device also prevents charge from being removed in locations where this is not desired when the pulse is applied.

Abstract: A semiconductor body (2) has a first region (3) providing a current path to a first main electrode (4) and carrying a plurality of active device cells (5). The majority (5a) of the active device cells are connected to a second main electrode (6) for providing a main current path through the device between the first and second main electrodes (4 and 6). At least one remaining active device cell forms a monitor cell (5b) and is connected to a monitor electrode (7) for providing a monitor current path through the device between the first main electrode (4) and the monitor electrode (7). The one monitor cell (5b) is formed differently from the majority (5a) of the active device cells so as to be more susceptible to failure than the majority of the active device cells so providing an early warning of the imminent failure of the device enabling evasive action to be taken to inhibit failure of the entire device.

Abstract: A semiconductor switch includes a power FET and a temperature sensor for providing a control signal to switch off the power FET when it reaches a predetermined thermal condition, such as a particular temperature. The power FET consists of a semiconductor body having a first region (13) of a first conductivity type adjacent one major surface (10a) thereof, and a plurality of cells (11). Each such cell has a second region (32) of the second (opposite) conductivity type provided within the first region (13), a third region (33) of the first conductivity type formed within the second region (32), and an insulated gate overlying a conduction channel in the second region (32) between the first and third regions (33 and 13). The temperature sensor (2) is formed within the semiconductor body (10) and consists of a number of further cells (11') of the same structure as the cells (11) of the power FET.

Abstract: A D.C. current compensation circuit for a nonlinear amplifier includes a compensating amplifier of substantially the same circuit configuration as that of the nonlinear amplifier, and a current mirror for coupling the compensation amplifier to the nonlinear amplifier to be compensated. The compensating amplifier is provided with feedback from its output to its input, so that a D.C. current provided to the output of the compensating amplifier can be used to compensate the D.C. input current of the nonlinear amplifier. In this manner, the nonlinear amplifier can be compensated for changes in gain due to temperature or manufacturing process variations.

Abstract: The invention relates to a semiconductor diode laser whose strip-shaped active region is limited by an end face which is curved for forming a lens of a given strength. A disadvantage of the known diode is that it has a comparatively high starting current. This is found to be caused inter alia by the etching necessary for forming a curved end face. During etching, unevennesses arise in the curved end face where scattering of the generated radiation occurs. This increases the starting current of the diode. A diode according to the invention is characterized in that the curved end face is covered with a covering layer of a material having a refractive index different from that of the active layer, and the refractive index of the covering layer and the curvature of the end face are so chosen that the scattering of the generated radiation is a minimum for the given strength of the lens.

Abstract: A method of manufacturing a semiconductor device includes the step of providing a reaction chamber (3) in which a layer of material (2) is deposited on a semiconductor slice (1) which is placed on a support (4) in the reaction chamber, a process gas being conducted towards the slice (1) through a gas inlet system (6) which is provided with a perforated gas inlet plate (9) arranged opposite the support (4). The reaction chamber is, between depositions, periodically cleaned through generation of a plasma between the support (4) and the gas inlet plate (9) in a gas mixture comprising fluorine or a fluorine compound and oxygen or an oxygen compound. A portion of the gas mixture which is comparatively rich in oxygen is conducted into the reaction chamber through the gas inlet system (6) with the gas inlet plate (9), while a portion of the gas mixture comparatively poor in oxygen is conducted into the reaction chamber through an auxiliary inlet system (23).

Abstract: A semiconductor memory device includes an array of rows and columns of field effect transistors (FETs) which provide memory locations. The FET gate electrodes in each row are connected to a respective row conductor and the FET first and second main electrodes in each column are connected to respective adjacent column conductors so that the second main electrodes in one column are connected to the first electrodes of the FETs in any adjacent column. Circuitry is provided for storing data at and reading data from the memory locations. The circuitry stores data at a desired memory location by applying a first predetermined voltage V.sub.g.sup.W to a selected row conductor and a second predetermined voltage V.sub.d.sup.

Abstract: A word oriented processing system includes a processing unit and a ferroelectric memory having a plurality of memory units organized in a matrix of rows and columns. Each memory unit stores a processor dataword of, for example, 8 or 16 bits, and contains a plurality of serial arrangements of, successively, a bitline connection, a first switching element, a ferroelectric capacitor and a node. The serial arrangements have the node in common. The node is connected to a plateline connection of the unit via second switching element. The processor reads or writes all bits of a word from one memory unit at a time. During reading or writing in one memory unit the first and second switching elements isolate the capacitors in other memory units from pulses on any of their plates.

Abstract: The television receiver includes a text generation mechanism which is capable of superimposing text on a received picture. In order to make the text more legible, while still retaining picture information a reduced contrast area is formed around the text. In order to superimpose the text on the picture text, RGB signals are applied to the video output circuits together with a switching signal (VDS) which causes either text or picture signals to be applied to the display device. To provide a reduced contrast area around the text display the switching signal (VDS) is arranged to switch between the picture signal and blanking level at a fast rate, for example at the clock rate, to produce the reduced contrast area.

Abstract: Power transistors used as high-side power switches are typically subjected to a variety of potentially destructive conditions, such as loss of bias current or loss of a ground connection in associated control circuitry. In order to protect the power transistor upon occurrence of such a potentially destructive condition, a control electrode disable circuit is provided to ensure that the power transistor will be turned off upon the occurrence of such a condition, or when the control circuits are deliberately turned off or placed in a standby mode. Turn-off of the power transistor is ensured by shunting a disable transistor across the input of the power transistor, and providing a disable circuit for activating the disable transistor in the event of loss of bias or loss of ground in the control circuitry. Reliable activation of the disable transistor is ensured by a bootstrap capacitor circuit in the disable circuit.

Abstract: A method of manufacturing a semiconductor device includes the step of providing a dopant (4) near a surface (2) of a semiconductor body (1) in a deposition step, after which in a diffusion step the dopant (4) is diffused into the semiconductor body (1) by keeping the semiconductor body (1) at an elevated temperature for a certain period in a furnace (11) while a process gas (13) is being passed through the furnace (11), after which any oxide layer (8) formed on the surface (2) is removed. A small amount of a hydrogen halide is added to the process gas (13), and it has been found that the creation of lattice dislocations in semiconductor devices is reduced thereby because impurities which play a part in the creation of lattice dislocations react with the hydrogen halide and are removed.

Abstract: A semiconductor device includes a number of programmable elements arranged in a matrix of rows and columns. The elements each have a doped semiconductor region (10) and a conductor region (20) which are mutually separated by an insulating layer (8). The conductor region (20) can be a material suitable for forming a rectifying junction (35) with the material of the semiconductor region (10). Within a row, the conductor regions of the programmable elements present therein are coupled to a common row conductor (21 . . . 23), and within a column the semiconductor regions of the programmable elements situated therein are connected to a common column conductor (11 . . . 14). To program an element, a programming voltage V.sub.

Abstract: It is possible to limit the voltage across a diode to the level of the pinch-off voltage of a JFET in an integrated circuit by connecting the diode in series with the JFET. As a result, the voltage offered through the JFET can be higher than the breakdown voltage of the diode, which is of particular importance in high-voltage ICs in which a highly doped buried zone is formed below the diode for reducing leakage currents to the substrate. According to the invention, the JFET together with at least one further circuit element is formed in a common island surrounded by an island insulation region. The gate of the JFET extends along the edge of the island and is separated from the relevant portion of the island insulation region substantially only by the source of the JFET. In the pinch-off condition, the gate divides the island into a high-voltage portion and a low-voltage portion which is coupled to the diode.

Abstract: A balun circuit comprising a first signal source connected across a first inductive means and connected to the latter a first capacitive means. To that network are connected a second signal source, a second inductive means, and a load to be matched to the signal sources. With the right choice of component values to produce a resonant condition, a balun that interfaces two balanced signal sources to an unbalanced single-ended load results capable of low insertion loss, arbitrary impedance transformation ratio, testability in the form of a 50 ohm port for in-circuit power monitoring and circuit characterization, class E operation, and easy implementation, as only standard L and C components are necessary. The circuit is reversible for connecting a single source to a balanced load.