Abstract: A semiconductor device, such as a gate turn-off thyristor, has, at a major surface of a semiconductor body a plurality of electrode fingers alternately contacting opposite conductivity type regions (e.g. the cathode and gate) of the semiconductor body. In order to save useful semiconductor area and to allow an improved electrode geometry bonding pads for the electrodes are formed at a level above the electrodes. An insulating layer separates the bonding pads and the electrodes. A first bonding pad contacts a first set of electrode fingers through a first set of windows in the insulating layer and a second bonding pad contacts a second set of electrode fingers through a second set of windows. In operation, the voltage drop along each electrode finger of a set is substantially equal. A third bonding pad may also contact the second electrode set through a third set of windows in the insulating layer.

Abstract: When two indirect only slightly different semiconductor materials having a suitable band gap, for example, AlAs and Al.sub.0.8 Ga.sub.0.2 As, are grown epitaxially one onto the other in layers of a few unit cell layers thick, the electronic band structures are folded so that the indirect minimum of the conduction band is displaced from the edge of the Brillouin zone to the center. The two indirect materials then constitute a superlattice with a band transition with a band gap of 2.2 eV.

Abstract: The invention relates to an EPROM or an EEPROM in which the information is stored in the form of electrical charge above the channel region of a MOST, as a result of which the threshold voltage of the MOST is determined by the stored information. Writing/erasing of the memory generally requires high voltages to cause charge current to flow through an insulating layer to and from the charge storage region. In order to avoid having the parasitic MOSTs becoming conductive, means are provided by which during operation a small reverse bias is applied to the sources of these parasitic transistors, as a result of which due to the high k factor the threshold voltage of the parasitic transistors increases considerably. This does not require additional logic because use can be made of the generator in the reading circuit, which generates a suitable small voltage.

Abstract: A current source arrangement includes a first and a second transistor arranged in cascode between an output terminal and the negative power-supply terminal. The arrangement further includes a current mirror circuit, a current source connected to the positive power-supply terminal being connected to an input current path which comprises a third transistor connected as a diode, a fourth transistor connected as a diode, and the collector-emitter path of a fifth transistor, which input current path is coupled to a second current path comprising a sixth transistor whose base is connected to the base of the third transistor, a resistor, and a seventh transistor connected as a diode, whose base is connected to the base of the fifth and the second transistor. Further, the base of the first transistor is connected to the emitter of the sixth transistor.

Abstract: By the use of high-ohmic polycrystalline silicon(poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Abstract: By the use of high-ohmic polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Abstract: A transconductance amplifier includes a differential amplifier, whose collector load is a current mirror having a current output. A current-source transistor arranged in the common emitter line supplies a current having a positive temperature-dependence. This current is obtained from a current-stabilizing circuit. By means of a voltage divider a fraction of a temperature-independent voltage is applied between the control electrodes of the differential amplifier, which voltage is taken from a voltage-stabilizing circuit. Depending on the value of this fraction, the output current is temperature-independent or has a negative temperature-dependence.

Abstract: By the use of high-resistivity polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Abstract: A non-volatile memory cell of the MNOS type, in which the sidewalk effect is avoided or at least considerably reduced by limiting the extension of the boundary layer, in which charge is stored, to a region which is smaller than the thin gate dielectric covered by the gate electrode. The gate electrode extends from the active region over a thin insulator, in which no charge storage takes place, to above the thicker field insulation.

Abstract: In an improved method for growing an oxide layer on a silicon surface of a semiconductor body, the semiconductor body is first provided with a silicon surface. A first oxide layer portion is then grown over the silicon surface in a first thermal oxidation process at a temperature of less than about 1000.degree. C. The semiconductor device is then annealed in a nonoxidizing ambient at a temperature above about 1000.degree. C., and finally a second oxide layer portion is then grown over the first oxide layer portion in a second thermal oxidation process to complete the growth of the oxide layer. The silicon surface may be of either polycrystalline or monocrystalline material. This method avoids both the dopant outdiffusion problems associated with present high-temperature oxidation processes and the stress-related irregularities associated with known low-temperature oxidation processes.

Abstract: In a 4-phase CCD with 90.degree. overlap of the clock voltages, the area below two clock electrodes may be used for the storage of charge packets which thus can be 2.times. as large as in conventional modes of operation. By choosing the penultimate electrode before the reading stage to be approximately 2.5.times. as large as the other electrodes, this double charge packet can be transferred undivided in time to the output diode, a feature which is particularly advantageous for further signal processing.

Abstract: In a current source circuit, a first and a second PNP transistor have commoned base electrodes, their emitters being connected through resistors to the positive supply voltage terminal. The collector lead of the first transistor includes a current source, which supplies a current which is reproduced at the output terminal. The commoned base electrodes are driven by a third transistor connected as an emitter follower, its emitter lead including a current source. The base of the third transistor is connected through a resistor to the positive supply voltage terminal as a result of which supply voltage variations appear also at the commoned bases of the first and second transistors so that the output current at the output terminal is substantially independent of supply voltage variations.

Abstract: An insulated-gate field-effect transistor which may be of a vertical power D-MOS type includes surface-adjacent source and emitter regions surrounded in a semiconductor body by a surface-adjacent second region of opposite conductivity type. A third region adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of these second and third regions is located in a main current path from the source region to a drain of the transistor, and an insulated gate, which may be of metal-silicide, capacitively controls a conductive channel at least in this part of the second region. The emitter region is located at a side of the source region remote from the channel part and is separated therefrom by an intermediate part of the second region. The source region is electrically connected to this intermediate part, for example by a short-circuiting metal-silicide layer.

Abstract: A semiconductor cathode is provided with deflection electrodes, with which a dipole field can be generated. As a result of this, electrons released at the surface of the semiconductor cathode leave the surface at a certain angle. For use inter alia in camera tubes, display tubes, such an inclined beam can be aligned without any problems. Positive ions which are released inter alia from residual gases and are accelerated in the direction of the cathode impinge on the cathode at an acute angle. As a result of this, the active part of the cathode is substantially not attacked by said positive ions, so that degradation is prevented.

Abstract: A dynamic two-phase circuit arrangement includes two dynamic switching circuits, each of which has an input stage, a non-inverting output stage and an inverting output stage. Two-phase control of the two dynamic switching circuits is effected by two drive pulses. The arrangement also includes combinatorial logic which is operated by the drive pulses to feed counter clock pulses to the first dynamic switching circuit. The first dynamic switching circuit performs a divide-by-two operation in response to the clock pulses and drives the second dynamic switching circuit from its Q-output. The second dynamic switching circuit includes an additional switching transistor which is also driven from the Q-output of the first dynamic switching circuit. This transistor is connected to perform an OR-function with the non-inverting output stage of the second dynamic switching circuit. As a result, this output stage produces shift pulses having half the repetition frequency of the clock pulses.

Abstract: In order to increase the breakdown voltage of a reverse-biased p-n junction of a semiconductor device, at least three annular regions which extend around the active device region are located within the spread of a depletion layer from the junction. At least one inner annular region is wider than outer annular regions, and this increased width of the inner region or regions reduces peak electrostatic fields found to occur at the bottom outer corners of the active device region and inner annular regions. The spacing of the annular regions increases with remoteness from the active device region, although at least two inner annular regions may have the same spacing as that of the innermost annular region from the active device region. A group of annular regions may have the same width as each other in the group.

Abstract: A data entry keyboard apparatus comprises a key-switch array (900) and associated electronic logic circuits (941). The key switches (901) of the array are so interconnected with each other and with connection terminals (902) to (905) of the logic circuits (941) that any one of these connection terminals can be interconnected with any other one by the actuation of an appropriate key-switch. The logic circuits (941) have a first set of coincidence gates (912) one for each key-switch (901). One input of each of these gates is connected to receive a particular one of a plurality of pulse signals of different phases produced by a pulse sequencer (906). A second input of each of these gates is connected to receive the same pulse signal via the key-switch array when the appertaining key-switch (901) is actuated. The coincidence or detection at an AND-gate of the same pulse signal at both inputs produces an output signal signifying actuation of the appertaining key-switch. The apparatus has n/2.times.

Abstract: An analog current switch in bipolar technology in which an intermediate transistor (T.sub.i), which isolates the current injector (S) from the switching diode (D.sub.c), is biassed by means of a transistor (T) whose collector, which is coupled to its base, is connected to the base of the intermediate transistor (T.sub.i) and to the anode of a diode (D), the emitters of (T) and (T.sub.i) as well as the cathodes of (D) and (D.sub.c) being interconnected.

Abstract: A recursive digital filter includes a first circuit 1 including a cascade arrangement of a magnitude truncation quantizing arrangement and an adder 6, 8. The first circuit has an output 5, and also inputs 3 and 4, output 5 being connected to the input 3 via a second circuit 10 and to the input 4 via a third circuit 11. Both last-mentioned circuits are formed by a cascade arrangement of an auxiliary circuit 12 and 14, respectively, and a multiplier arrangement 13 and 15, respectively. The auxiliary circuit 12 has a transfer function H.sub.1 (z)=p/(z-1) and the auxiliary circuit 14 has a transfer function H.sub.2 (z)=q/(z+1), wherein p and q represent constants.

Abstract: Two current circuits are between two common terminals (+V.sub.B and -V.sub.B). The ratio between the currents in the two current circuits is defined by a first current-dividing circuit, and the absolute values of these currents are defined by means of a second current-dividing circuit, in particular a resistor in this second current-dividing circuit. In order to ensure that the current-stabilizing assumes the proper state upon activation, a first current-supply circuit is coupled to the input of the second current-dividing circuit, which current-supply circuit comprises the series arrangement of a resistor and a transistor arranged as a diode, and a second current-supply circuit is coupled to the output of the current-dividing circuit, which second current-supply circuit includes a transistor whose base is connected in common with that of the transistor of the first current-supply circuit.