Patents Represented by Attorney, Agent or Law Firm Steven R. Biren
  • Patent number: 4697111
    Abstract: An integrated logic circuit includes a push-pull amplifier stage, in which by means of a bootstrap circuit the potential at the gate of the "push" transistor is brought above the supply voltage so that the output voltage of the amplifier lies above the supply voltage minus the threshold voltage of the push transistor. In order to prevent the charge from leaking away after the bootstrap capacitance has been charged via an enhancement transistor, the enhancement transistor is cut off by means of the "low" input signal. A second bootstrap circuit (between the input and the gate of the enhancement transistor) ensures that the first bootstrap capacitance is charged up to the full supply voltage because the latter gate electrode is lifted above the supply voltage by the second bootstrap.
    Type: Grant
    Filed: February 7, 1985
    Date of Patent: September 29, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Adrianus T. Van Zanten, Hendrikus J. M. Veendrick, Leonardus C. M. G. Pfennings, Wilhelmus C. H. Gubbels
  • Patent number: 4695865
    Abstract: A semiconductor device includes insulated gate field effect transistors, with which logic gate circuits having a satisfactory switching speed and a high packing density can be realized. The logic gate circuits are composed of transistor structures having a common source zone (22), which each comprise a gate (33), a second semiconductor zone (25) and one or more drain zones (28) and are manufactured in DMOS technology. The gates are strip-shaped or have at least a strip-shaped part. The gate circuits can be integrated in a simple manner with one or more high-voltage transistors manufactured in DMOS technology.
    Type: Grant
    Filed: April 4, 1985
    Date of Patent: September 22, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Kornelis J. Wagenaar
  • Patent number: 4695753
    Abstract: The invention relates to a charge detector, more particularly for reading binary information in a CTD. The detector includes a flipflop having two cross-coupled MOS transistors and two MOS transistors acting as loads. The signal to be read and the reference signal are supplied to the gates of the loads. The junctions between the driver transistors and the loads are connected to reset transistors. The drains of the loads are applied to a (fixed) supply voltage and the sources of the driver transistors are applied via a switching transistor to the supply voltage return. The circuit arrangement is operated so that before the activation of the flipflop the said junctions are set to a signal-dependent preadjustment. When the switching transistor is then energized, the flipflop will be in the correct stage with a higher degree of reliability and without being influenced by clock cross-talk.
    Type: Grant
    Filed: September 18, 1986
    Date of Patent: September 22, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Marcellinus J. M. Pelgrom
  • Patent number: 4692208
    Abstract: On a support which supports a light-emitting semiconductor device there is arranged a cap which is hermetically sealed to the support. In the cap there is provided a transparent plate, an inner layer of which facing the semiconductor device consists of a material having a high refractive index (>1.7). On the outer side of the plate there is provided a layer of photosensitive lacquer which is exposed to the light emitted by the semiconductor device. After development of the layer of lacquer, only the exposed part which is situated opposite the semiconductor device remains. This part is heated to the melting point, thus forming a droplet of lacquer, after which the outer layer of the plate and the droplet of lacquer are removed by way of a non-selective etching method, so that a lens which is situated opposite the semiconductor device and a flat window which surrounds the lens are automatically formed at the same time.
    Type: Grant
    Filed: September 26, 1984
    Date of Patent: September 8, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Giok D. Khoe, Henricus M. De Vrieze
  • Patent number: 4691127
    Abstract: In an adaptive electronic buffer system in which a set circuit generates logic set signals for the buffer circuits, parallel sub-buffers are switched on or off by the set signals, so that the specified charging and discharging times of the output can be achieved. This setting compensates for the manufacturing process variations and operating conditions (temperature, supply voltage) of the buffer circuits. The spread in the output conductance is reduced, thus reducing the risk of fast current variations, inductive voltage peaks and the associated loss of data.
    Type: Grant
    Filed: November 25, 1985
    Date of Patent: September 1, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Cornelis M. Huizer
  • Patent number: 4691218
    Abstract: A charge transfer device has a charge transfer channel and at least one second storage site situated outside this channel, whereby a connection channel for transferring charge packets is present between a first storage site situated in the charge transfer channel and the second storage site, which connection channel can be controlled by a transfer electrode. The transfer electrode is strip-shaped and extends in the longitudinal direction of the charge transfer channel. According to the invention, the transfer electrode essentially lies beside the charge transfer channel and has at the area of an end of the connection channel a projection which ensures satisfactory charge transfer from the storage site to the connection channel.
    Type: Grant
    Filed: January 23, 1987
    Date of Patent: September 1, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Arnoldus J. J. Boudewijns
  • Patent number: 4689655
    Abstract: An integrated circuit or other semiconductor device, comprises a semiconductor body with a bipolar transistor consisting of electrically parallel transistor structures at least a number of which have a different value of emitter series resistance. The transistor emitter zone comprises a number of active emitter regions which constitute the emitters of the different transistor structures, a number of emitter contact regions contacted by emitter metallization via emitter contact windows, and a number of emitter connection regions which interconnect the emitter contact regions and the active emitter regions. The different values of emitter series resistance of the transistor structures are realized by having a different size or location with respect to the emitter connection regions for at least a number of the emitter contact windows, without necessitating a variation of the emitter zone geometry for each transistor structure.
    Type: Grant
    Filed: June 24, 1986
    Date of Patent: August 25, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Paul Sonnenberger
  • Patent number: 4680619
    Abstract: Two (polycrystalline) silicon tracks located at a relative distance of the order of submicrons which contact the subjacent semiconductor body with a pn junction formed therein, are connected to each other via a metal silicide track. The resulting shortcircuiting of the pn junction does not influence the operation of the circuit, for example, a memory cell, realized in the semiconductor body. By providing the whole conductor pattern with an oxide layer in which a contact hole is formed at the area of the shortcircuit, the latter can then be provided in a self-aligning manner.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: July 14, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Jan Lohstroh, Wilhelmus J. M. J. Josquin
  • Patent number: 4677634
    Abstract: A semiconductor laser of the double heterojunction (DH) type having a current-confining buried blocking layer. According to the invention, a high-resistance region having a disturbed crystal structure is present outside and on either side of the strip-shaped active region and extends at least throughout the thickness of the blocking layer. As a result, the lateral leakage currents and the parasitic capacitances are reduced so that the laser can be used at frequencies considerably higher than 1 GHz. The high-resistance region is preferably obtained by protron bombardment. The invention is particularly advantageous in DCPBH lasers for optical communication.
    Type: Grant
    Filed: March 21, 1985
    Date of Patent: June 30, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Lambertus J. Meuleman, Adriaan Valster
  • Patent number: 4670966
    Abstract: A semiconductor laser having mirror faces serving as resonators, in which the active laser region (2) includes end zones adjoining the mirror faces which have implanted ions, preferably protons, with associated crystal damage. The end zones have a length which is at least equal to the diffusion length of the recombining charge carriers in the end zones. As a result of the high recombination rate in the end zones substantially no non-radiating recombination occurs at the mirror faces so that mirror erosion is avoided.The invention relates to a method in which the end zones are formed by an ion bombardment on the upper surface of the semiconductor wafer with a number of lasers, which wafer at the area of the mirror (cleavage) faces to be formed is provided with grooves which do not extend up to the active layer, in which grooves the end zones are provided via an ion bombardment through the active layer.
    Type: Grant
    Filed: September 23, 1985
    Date of Patent: June 9, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Johannes A. De Poorter, Peter J. De Waard, Rudolf P. Tijburg, Gerardus L. Dinghs
  • Patent number: 4670731
    Abstract: A temperature sensor in the form of a temperature-dependent semiconductor resistor operating according to the current-spreading principle includes a semiconductor body of one conductivity type of silicon, which is provided on its lower side with a conductive layer and is provided on its upper side with at least one contact zone of the one conductivity type. The upper side is coated with a silicon oxide layer or a silicon nitride layer. In order for the given resistance value to be maintained more accurately and the temperature coefficient to have only a small spread, the semiconductor body is provided at its surface adjacent the silicon oxide layer or silicon nitride layer with a surface zone of the opposite conductivity type. Thus, it is possible to limit to a minimum value or to completely compensate for the influence of charges at the silicon oxide layer or silicon nitride layer.
    Type: Grant
    Filed: August 16, 1985
    Date of Patent: June 2, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Heinrich Zeile, Hartmut Witt
  • Patent number: 4669100
    Abstract: A series-parallel-series memory or other parallel-to-series CCD has charge-signals interlaced in alternate parallel channels 1a and 1b, and de-interlacing electrodes (19, 20, 21, 22) at the parallel-to-series transition. In order to avoid delay effects as a result of comb-shaped electrode configurations of the de-interlacing electrodes, and associated complex clock control, a narrow extra electrode (41) is provided between the de-interlacing electrodes and the series-output register (B). This electrode (41) may serve as a buffer electrode for each half row of information (from 1a or 1b) while the preceding half row (from 1b or 1a) is transported through the series output register.
    Type: Grant
    Filed: September 22, 1986
    Date of Patent: May 26, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Jan W. Slotboom, Hendrik A. Harwig, Marcellinus J. M. Pelgrom
  • Patent number: 4661725
    Abstract: An elementary logic circuit obtained by means of Schottky barrier field effect transistors of gallium arsenide includes a differential amplifier, whose first branch, controlled by the input signal E, supplies an output signal S.sub.1, and whose second branch, controlled by a reference signal, supplies an output signal S.sub.2. This circuit further includes two paired level translator stages, the first of which supplies output signal S and the second of which supplies a complementary signal S, the output signal S constituting the reference signal which controls the second branch of the differential amplifier. The circuit can advantageously be used in high-speed IC modules having a lower power consumption, consisting of gallium arsenide and compatible with the circuits realized according to the ECL 100 K technology on silicon.
    Type: Grant
    Filed: February 7, 1985
    Date of Patent: April 28, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Bernard Chantepie
  • Patent number: 4653057
    Abstract: A semiconductor device for producing or amplifying electromagnetic radiation, more particularly a semiconductor laser, has a substrate which has a mesa-shaped raised portion. On either side of the mesa there is located a blocking layer of a conductivity type opposite to that of the substrate. On the blocking layer are formed a first passive layer of the same conductivity type as the substrate, an active layer and a second passive layer of a conductivity type opposite to that of the substrate. According to the invention, the blocking layer also extends over the mesa, which is connected by diffusion from at least the first passive layer to the blocking layer.
    Type: Grant
    Filed: March 30, 1984
    Date of Patent: March 24, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Theodorus G. J. van Oirschot
  • Patent number: 4652899
    Abstract: The capacitance of a radiation-sensitive diode can be considerably reduced by giving it the form of a pn junction (4) between a first semiconductor region (4) and a layer-shaped semiconductor zone, which in operation is fully depleted. The speed of such a diode is favorably influenced by the choice or the shape of the geometry of the layer-shaped zone. When the latter is formed with parts decreasing in width of thickness, an electric field is produced in these parts which accelerates the transport of minority charge carriers to a central contact.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: March 24, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Arthur M. E. Hoeberechts
  • Patent number: 4651052
    Abstract: A device for picking up or displaying images includes a semiconductor device having at least one cold cathode. The semiconductor device is mounted to the outside of the device for picking up or displaying images by being fixed to a support having an opening to permit the passage of electrons from the semiconductor device to the interior of the devices for picking up or displaying images. This mounting configuration offers the advantages of simple cooling of the semiconductor device, direction connection of the semiconductor device, and improved electro-optical performance.
    Type: Grant
    Filed: July 10, 1985
    Date of Patent: March 17, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Arthur M. E. Hoeberechts
  • Patent number: 4651181
    Abstract: A semiconductor device includes a semiconductor body in which a field effect transistor is formed which is composed of a number of parallel-connected subtransistors. Each subtransistor comprises a polygonal box-shaped cell of the semiconductor body. These cells each comprise a first semiconductor zone embedded in the semiconductor body and a second semiconductor zone embedded in the first zone. The peripheral part of the semiconductor body surrounding the first zone serves as a drain zone of the subtransistor, while the second zone serves as a source zone and a narrow edge strip of the first zone lying between the second zone and the peripheral part serves as a channel zone. The peripheral part comprises strip-shaped parts which extend in the direction of a central part of the first zone. The transistor has a comparatively low resistance in the switched-on state.
    Type: Grant
    Filed: February 6, 1986
    Date of Patent: March 17, 1987
    Assignee: U. S. Philips Corporation
    Inventor: Gerard R. David
  • Patent number: 4649554
    Abstract: In a charge transfer device in accordance with the invention, the channel is subdivided at the area of the output into two subchannels provided with separate output gates which are clocked in phase opposition, and with separate reset gates which are likewise clocked in phase opposition. Between the output gates and the reset gates there is arranged a floating gate common to both subchannels by which signals can be read during 100% of a clock period so that no additional filtering operations for filtering out spectra of higher order are required. This output circuit can be used in applications in which high speeds and a high sensitivity are required.
    Type: Grant
    Filed: January 15, 1986
    Date of Patent: March 10, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Arnoldus J. J. Boudewijns, Leonard J. M. Esser
  • Patent number: 4646116
    Abstract: A semiconductor device includes an electroluminescent diode, which is obtained from at least one epitaxial layer of a III-V compound vapor-deposited on a substrate which is also of a III-V compound. The invention is characterized in that, preferably before the epitaxial layer is vapor deposited, a layer having a disturbed crystal structure is provided at the surface of the substrate, as a result of which the substrate does not generate radiation.
    Type: Grant
    Filed: November 28, 1984
    Date of Patent: February 24, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Jacques J. Varon, Marie-Josephe Martin, Marc Mahieu
  • Patent number: 4646115
    Abstract: Separate areas of an active unipolar barrier, e.g. a Schottky barrier, of a semiconductor device are located between closely-spaced field-relief regions which provide the device with an improved voltage blocking characteristic. The flow of minority carriers into the adjacent body portion under forward bias is restricted by providing, at least at the areas of the field-relief regions, a layer of different material from that of the body portion and from that of the unipolar barrier-forming means. The layer of different material may form a high-impedance electrical connection with the field-relief regions, and/or it may form with the body portion a heterojunction such as, for example, a Schottky barrier of higher barrier height, a barrier between different band gap materials or a MIS structure, which heterojunction forms part of the field-relief regions.
    Type: Grant
    Filed: May 1, 1986
    Date of Patent: February 24, 1987
    Assignee: U.S. Philips Corporation
    Inventors: John M. Shannon, John A. G. Slatter, David J. Coe