Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.

Abstract: An integrated semiconductor circuit includes an output stage and a control circuit. The output stage comprises several (e.g. four) pull-down output transistors, which are sequentially switched on for pulling down the output node, whereby four small current steps are made instead of one high current step. As a result the package inductance generated power supply line noise will be substantially reduced (by at least a factor four). The same technique can be used for limiting the supply line noise due to the charge current for charging the output node via pull-up transistors.

Abstract: A TTL to CMOS-input buffer has minimal sensitivity of threshold level variation with changes in device parameters. In particular, the design is insensitive to P-channel characteristics over very wide ranges of transistor threshold voltages and gain parameter spreads.

Abstract: In a filter arrangement, a first junction capacitor is arranged between the inverting output and the non-inverting input of a fully balanced amplifier and a second junction capacitor is arranged between the non-inverting output and the inverting input. Additionally, a first resistor is arranged between a first input terminal and the non-inverting input and a second resistor is arranged between a second input terminal and the inverting input. A first current source is connected to the non-inverting input and a second current source is connected to the inverting input. The current sources produce the reverse voltages for the junction capacitors across the resistors to define the capacitance values of these capacitors.

Abstract: An integrated logic circuit includes an output circuit for generating an output current which increases linearly in time. In integrated logic circuits the problem presents itself that the rapid variation of the (dis) charging of a data output causes a reverse voltage pulse VL across the inductance formed by the connection wires. The reverse voltage is limited by causing the charge or discharge current (for the load capacities present) to increase linearly to a maximum permissible value. This is done by driving the output field effect transistor with a control voltage VC which varies in time in the form of a square root.

Abstract: The invention relates to a logic MOS gate of the domino type, having a precharging transistor, a validation transistor and logic transistors. To prevent unwanted discharging of a precharged high level, which may be induced by at least one input data being stabilized too slowly, that is to say not before a clock signal has risen to the high level, a p-MOS sub-network is arranged in parallel with the source-drain path of the precharging transistor and receives at least the input data which was too slowly stabilized in such a manner as to establish a conductor path which reestablishes the precharged high level.

Abstract: In a filter arrangement having a transconductance circuit, a first capacitor is arranged between the inverting output and the non-inverting input of a balanced amplifier and a second capacitor is arranged between the non-inverting output and the inverting input. The outputs of a transconductance circuit (transconductor) are connected to the non-inverting input and the inverting input, which transconductor converts a balanced input voltage applied to the inputs into a balanced output current, its transconductance being variable by means of a variable current source. Further, the transconductor is loaded by a load circuit comprising a first current-source transistor and a second current-source transistor whose common base is connected, via a diode, to the junction point between two resistors arranged between the outputs of the transconductor.

Abstract: A differential amplifier circuit for regenerating complementary analog signals of low amplitude includes a differential pair of field effect transistors whose common sources are connected to a first supply voltage V.sub.SS via a load, a pair of loads which are connected to the drain of each transistor of the differential pair and to a second supply voltage, respectively, and a level regenerating circuit having a pair of diodes for deriving the signals from the drain of each transistor of the differential pair. The signals transported by the diodes are applied to the lower transistor of a pair of push-pull stages whose upper transistor directly receives the signal derived from the drain of the other transistor of the differential pair, while the source of the lower transistors of the push-pull stages is connected to ground and the drain of the upper transistor of these stages is connected to the second supply voltage V.sub.

Abstract: A select buffer circuit includes a first inverter circuit, a second inverter circuit connected to the first, and a circuit for charging and discharging the base of an inverter transistor in the second inverter circuit from a node in the first inverter circuit. The charging and discharging circuit includes a Schottky diode connected to the inverter transistor, a Schottky transistor connected in series with the diode, and a resistor for coupling the base of the Schottky transistor to the node in the first inverter circuit. A bipolar multiplexer including the select buffer circuit offers the advantage of an improved output waveform.

Abstract: A high voltage semiconductor device includes a two-dimensional array of polygonal regions in a higher resistivity body portion of the opposite conductivity type. The p-n junction between these regions and the body portion may be, for example, a drain junction of a D-MOS transistor or a collector junction of a bipolar transistor and is reverse-biased in at least a high voltage mode of operation. In order to relieve the high electric field at the corners of the polygonal regions, a plurality of further regions is distributed in each area of the body portion between facing corners of three or more of the polygonal regions. These further regions of the same conductivity type as the polygonal regions are located on at least one line from each of these corners in a symmetrical arrangement of the further regions within each area.

Abstract: In integrated circuits the delay of the signal transitions has to lie within specified limits. This delay is partly determined by variations in the manufacturing process (process scatter). To compensate for the effect of this scatter a load capacitance is connected via a switching element to a node which is to be influenced in the integrated circuit. The switching element receives a reference voltage which is dependent on the manufacturing process and is generated by reference source, so that the node capacitance 26 is connected to the node for a longer or shorter time, depending on the process scatter.

Abstract: The invention relates to a CCD having a diode cut-off input, a reference voltage being applied to the input diode and the input signal being supplied to an input gate located in front of the first clock electrode. If the electrodes are composed of a transfer part and a storage part with an incorporated potential difference, it is possible that incomplete charge transport may occur from the input to the first clock electrode. In order to avoid this incomplete charge transport and/or to be able to enlarge the dynamic range of the input signal, a larger clock voltage, for example 10 V, is applied to the first clock electrode than to the following clock electrodes, which receive, for example, 5 V. In a preferred embodiment, the 5 V clock voltage can be supplied for this purpose by a boots-trap circuit ot the first clock electrode.

Abstract: The invention relates to a CCD having a so-called diode cut-off input, in which the input diode is applied to a reference voltage and the input signal is supplied to the input gate located in front of the first clock electrode. More particularly, if the electrodes are composed of a transfer part and a storage part with an incorporated potential difference, it is possible that, when charge is transported from the input gate to the first clock electrode, a large amount of charge is left behind. In order to avoid this and/or to be able to enlarge the dynamic range of the input signal, a MOST switch controlled by the same clock voltage as the first clock electrode is arranged between the input gate and a reference voltage, for example ground. This switch becomes conducting when the charge is transferred, as a result of which the potential level below the input gate can be adjusted above the surface potential below the transfer part of the first clock electrode.

Abstract: A complementary Silicon-On-Insulator (SOI) Lateral Insulated Gate Rectifier (LIGR) is fabricated in a monocrystalline silicon layer provided on a major surface of a substantially insulating substrate. The monocrystalline silicon layer includes a number of adjacent, doped coplanar layer portions, with the complementary SOI LIGR device being formed of adjacent, contacting layer portions forming two complementary LIGR elements with a common source region. The common source region, as well as both of the drain regions of the device, are composed of regions of both the first and second conductivity types. In this manner, a simple, easily fabricated, balanced, high performance complementary LIGR structure is obtained in which undesired substrate currents are substantially eliminated.

Abstract: In a binary counter made using the I.sup.2 L technique, the realization of different gate types is complicated, because only NAND gates can be obtained directly. According to the invention, a particular circuit construction is indicated, which is constructed according to the I.sup.2 L technique, is very simple and requires only a few gate transit times so that a comparatively high switching speed can be attained. In the circuit construction of the invention, both the flipflops and their associated combinatorial networks are fabricated in the I.sup.2 L technique, using only NAND gates. Nevertheless, because of the particular circuit configuration of the invention, all of the necessary internal signals can be generated in an efficient manner.

Abstract: The invention relates to a semiconductor device of the hetero-junction transistor type comprising a stack of semiconductor layers which in combination constitute the source, drain and gate regions, while the current path between the source and drain regions is substantially at right angles to the various junctions. The gate region constitutes an electron accumulation region in the form of a two-dimensional quasi Fermi-Dirac gas which can be brought to the desired polarization potential of at least one gate electrode, while the electrons forming the source-drain current traverse this electron cloud without having a strong interaction with it, in ballistic or quasi-ballistic conditions.

Abstract: The invention relates to a matrix of light-emitting diodes and a method of manufacturing same. A matrix comprises highly doped contact lines of a first conductivity type, localization zones of the second conductivity type opposite to the first type extending transversely with respect to the semi-insulating zones arranged along lines and/or columns and separating along diodes an active layer in contact with the contact lines and a superficial injection layer. The contacts connect the diodes columnwise, regions being internally limited along lines by the area straight above the upper parts of the localization zones, and along columns by the semi-insulating regions. Thus, the contacts are entirely situated outside the light emitting zones defined by the localization zones. The method of manufacturing utilizes steps of localized etching and epitaxy.

Abstract: An elementary decoder circuit for a monolithically integrated static random access memory is constructed by means of gallium arsenide field effect transistors and formed by a NOR-gate whose n inputs receive the n coded addressing signals a.sub.1, a.sub.2, . . . , a.sub.n of the memory, or their complements, and whose output supplied a signal which is applied to the upper transistor of a push-pull stage as well as a complementary signal, obttained via an inverter transistor, which is applied to the lower transistor of the push-pull stage.

Abstract: A bipolar semiconductor device with interdigitated emitter and base regions has a sub-region of the base, which has a shorter carrier recombination time than the major part of the base region due to the presence of argon ion implantation induced carrier recombination centers. The sub-region of the base is located centrally with respect to the emitter region to intercept the transient current lines during device turn-off and so to promote collapse of the transient current and the avoidance of second breakdown of the device. The centrally located sub-region of the base is remote from the emitter region edges to collector region current flow when the device is on. The ions may be implanted at energies between 50 keV and 3 MeV and at doses between 10.sup.11 ions cm.sup.-2 and 10.sup.14 ions cm.sup.-2. The implanatation mask may be provided by photolithographically processed resist having a thickness between 0.5 .mu.m and 4 .mu.m dependant on the ion implantation energy.

Abstract: A semiconductor device has a surface zone which forms a planar pn junction with the surrounding substrate, this pn junction being biased in operation in the reverse direction. In order to increase the breakdown voltage, one or more floating zones are located beside the pn junction within the range of the depletion zone, which also form planar pn junctions with the substrate. According to the invention, the floating zones have an overall doping of at least 3.multidot.10.sup.11 and at most 5.multidot.10.sup.12 atoms/cm.sup.2, as a result of which they are substantially depleted at a high reverse voltage.