Patents Represented by Attorney, Agent or Law Firm Steven R. Biren
  • Patent number: 4750023
    Abstract: Semiconductor devices including one or more gate-controlled unipolar hot-carrier transistors have a semiconductor barrier region located between laterally-separated first and second region portions of one conductivity type. The barrier region has a net doping concentration of the opposite conductivity type and is sufficiently thin such that the depletion layers formed at zero bias with both the first and second regions substantially merge together to deplete the barrier region of mobile charge carriers. Current flow between the first and second region is at least partially by thermionic emission of charge carriers of the one conductivity type across the barrier region at a major surface of the body. The transistor has a gate in the vicinity of the barrier region and capacitively coupled thereto (for example via a dielectric layer) so as to permit the thermionic emission current to be controlled by applying a voltage to the gate to adjust the effective barrier height of the barrier region.
    Type: Grant
    Filed: June 5, 1987
    Date of Patent: June 7, 1988
    Assignee: U.S. Philips Corporation
    Inventor: John M. Shannon
  • Patent number: 4739389
    Abstract: In a high-frequency circuit arrangement, passive parts of the circuit are realized in a semiconductor body in which active circuit elements of another semiconductor material are located in recesses in the semiconductor body. When the semi-conductor body is at least in part low-ohmic, a reference plane, for example, the ground plane, can extend very close to the elements of the circuit arrangement. Consequently, due to the shorter connections required, parasitic effects are considerably reduced. When only one active element is mounted and only connections for this element are formed on the semiconductor body, a very suitable support for mounting and measurement is obtained.
    Type: Grant
    Filed: September 26, 1986
    Date of Patent: April 19, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Willem Goedbloed
  • Patent number: 4736273
    Abstract: A power semiconductor device for surface mounting includes an isolating body, a thermal dissipator and electrical connection pins. The pins and legs of the thermal dissipator extend in the direction of the lower surface of the body. During a surface mounting operation of the device on a substrate, a quantity of solder is enclosed by a capillary effect under the major part of the plate. Thus, a good electrical and thermal contact is obtained with a metallization of the substrate.
    Type: Grant
    Filed: September 25, 1986
    Date of Patent: April 5, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Bernard M. G. Vertongen, Andre M. Papoular
  • Patent number: 4731345
    Abstract: A method of making a semiconductor device for producing or amplifying electromagnetic radiation, more particularly a semiconductor laser, has a substrate which has a mesashaped raised portion. On either side of the mesa there is located a blocking layer of a conductivity type opposite to that of the substrate. On the blocking layer are formed a first passive layer of the same conductivity type as the substrate, an active layer and a second passive layer of a conductivity type opposite to that of the substrate. According to the invention, the blocking layer also extends over the mesa, which is connected by diffusion from at least the first passive layer to the blocking layer.
    Type: Grant
    Filed: December 31, 1986
    Date of Patent: March 15, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Theodorus G. J. Van Oirschot
  • Patent number: 4729007
    Abstract: A semiconductor device having the advantages of bipolar transistor characteristics (such as a low ON resistance) and of FET characteristics (such as a rapid turn-off) can be obtained by integrating and merging together in one semiconductor body a bipolar transistor T and two or more insulated-gate FETs T1 to T4. A lateral FET T1 is formed by providing a drain region adjacent to the base region of the bipolar T and an insulated gate overlying an intermediate channel area. A further FET T3 which is of complementary conductivity type to T1 may have a source region provided in the drain region and an insulated gate over a channel area between the source region and the emitter region of T. These insulated gates are connected together, for example as a common gate grid, so permitting T1 to be turned on to extract charge from the base region of the bipolar T during turn off when T3 is turned off to interrupt the terminal connection to the emitter region of bipolar T.
    Type: Grant
    Filed: September 17, 1985
    Date of Patent: March 1, 1988
    Assignee: U.S. Philips Corporation
    Inventor: David J. Coe
  • Patent number: 4727404
    Abstract: A field effect transistor for high-frequency applications includes, on a monocrystalline semi-insulating substrate, a thin active n-doped layer of a material having a high electron mobility, on whose surface are deposited two ohmic contacts forming the source and drawing contact regions of the transistor, between which a metallic contact constitutes a gate electrode of the Schottky type. According to the invention, the transistor is characterized in that a dielectric layer is deposited on the active layer between the source and gate electrodes on the one hand and between the gate and drain electrodes on the other hand, and in that the metallic layer constituting the ohmic contacts is continuously prolonged on this dielectric layer without causing a short-circuit with the gate.
    Type: Grant
    Filed: December 19, 1986
    Date of Patent: February 23, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Dominique Boccon-Gibod
  • Patent number: 4727457
    Abstract: The invention relates to an optoelectronic device for surface mounting of the type comprising an insulating substrate, whose upper surface receives at least one optoelectronic element electrically connected to contacts of the lower surface of the substrate through conductive strips. An annular spacer is fixed to the upper surface of the substrate. A spherical lens is glued on the annular spacer and the plane of light emission is situated at a distance from the spherical lens which is smaller than its extension.
    Type: Grant
    Filed: September 22, 1986
    Date of Patent: February 23, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Jacques C. Thillays
  • Patent number: 4724221
    Abstract: A method of manufacturing a semiconductor device having an integrated circuit in an epitaxial layer on a substrate in which the epitaxial layer comprises islands of conductivity type opposite to that of the substrate which are surrounded laterally by a surrounding region of the same conductivity type as the substrate, is disclosed. Both the islands and the surrounding region are formed by diffusion from buried layers through the epitaxial layer. A bipolar transistor is provided in at least one island. The p-n junctions between the islands and the surrounding region are substantially at right angles to the surface. The invention involves a method of manufacturing the device and is of particular importance for realizing very compact and fast circuits with low dissipation consisting of a combination of CMOS bipolar subcircuits.
    Type: Grant
    Filed: July 7, 1986
    Date of Patent: February 9, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems
  • Patent number: 4723229
    Abstract: The invention relates to a (static) memory which is divided into a number of memory blocks, memory cells being arranged in rows and columns in each memory block. A row in a memory block is activated via a selection gate whereto there are applied an inverted row selection signal (which is applied to all memory blocks) and a non-inverted and an inverted block selection signal (which is applied to all section gates in a memory block). The selection gate comprises a P-MOS transistor and two parallel-connected N-MOS transistors. The junction between the P-MOS and the N-MOS transistors constitutes the gate output (for activating a row of cells). The row selection signal is applied to the gate electrode of the PMOS transistor and of a first N-MOS transistor. The inverted block selection signal is applied to the gate electrode of the other N-MOS transistor and the block selection signal is applied to the main electrode of the P-MOS transistor.
    Type: Grant
    Filed: February 4, 1986
    Date of Patent: February 2, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Cornelis D. Hartgring, Frans J. List
  • Patent number: 4717855
    Abstract: The efficiency of a semiconductor cathode can be increased by bombarding the electron-emitting regions (8) with an electron beam (8), which frees the surface from adhered oxygen particles. The electron beam preferably originates from a second semiconductor cathode (42), which has an opening (42) for passing the electron beam (20) of the first semiconductor cathode (20). Alternatively, both semiconductor cathodes can be realized in one semiconductor body.
    Type: Grant
    Filed: February 26, 1986
    Date of Patent: January 5, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Jan Zwier, Johannes H. A. Vasterink
  • Patent number: 4717944
    Abstract: A semiconductor device including a field effect transistor, such as an insulated gate field effect transistor, which has in the direction from source zone to drain zone successive first and second channel zones with associated gate electrode parts. According to the invention, over at least 80% of the overall channel width, in a direction at right angles to the direction of source-drain current, the ratio L.sub.1 /L.sub.2 between the length L.sub.1 of the first gate electrode part and the length L.sub.2 of the second gate electrode part is variable and smaller than unity in order to improve the linearity of the field effect transistor.
    Type: Grant
    Filed: October 23, 1986
    Date of Patent: January 5, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Petrus J. A. M. Van de Wiel, Leonard J. M. Esser
  • Patent number: 4716317
    Abstract: In an integrated circuit of the type having a reset transistor for a capacitance succeeded by an active information charge transfer transistor for the capacitance, a clock pulse signal at the common switching electrode results in opposite-polarity switching. It is found in practice that a noise pattern present at a reset pulse level in the circuit output signal may cause problems in the case of further signal processing operations in the device. To solve these problems, a control method is used with a clock pulse signal which has three signal levels, a first level at which only the reset transistor is conducting, a second level at which the two transistors are both non-conducting, and a third level at which only the information charge transfer transistor is conducting.
    Type: Grant
    Filed: September 22, 1986
    Date of Patent: December 29, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Alphons F. E. B. Spierings
  • Patent number: 4716314
    Abstract: A high speed I.sup.2 L circuit having a topology which is based on a layout of parallel arranged gate circuits in which the inverter transistors of each gate circuit are arranged in a row and below the signal lines to which they are connected, said signal lies extending transversely to the rows, while the complementary transistors for the current supply of the inputs of the gate circuits are situated laterally beside the signal lines. Said layout facilitates the designing of comparatively compact I.sup.2 L circuits in which various measures to increase their speed can be taken, for example, the use of dielectric isolation, reduction of the input series resistance, reversal of the doping profile and the application of a potential difference between the bases of the complementary transistors and the common emitter of the inverter transistors.
    Type: Grant
    Filed: August 6, 1975
    Date of Patent: December 29, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Cornelis Mulder, Henricus E. J. Wulms
  • Patent number: 4716446
    Abstract: A semiconductor device comprising a field effect transistor of the lateral or vertical DMOST type having a source zone of the one conductivity type, an adjoining channel region of the other conductivity type, a drain zone of the one conductivity type and a weakly doped drift region located between the drain zone and the channel region. According to the invention a second gate electrode located on the side of the drain zone and separated from the first gate electrode is disposed on the insulating layer above the channel zone behind the first gate electrode located on the side of the source zone. The length L.sub.2 of the part of the second gate electrode located above the channel zone is at least equal to that of the part of the first gate electrode located above the channel zone. As a result, a high value of the mutual conductance g.sub.m as well as good linearity can be obtained.
    Type: Grant
    Filed: June 9, 1986
    Date of Patent: December 29, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Leonard J. M. Esser, Petrus J. A. M. Van de Wiel, Leonardus A. Daverveld, Johannes A. A. Van Gils
  • Patent number: 4712124
    Abstract: A complementary Lateral Insulated Gate Rectifier (LIGR) includes two complementary LIGR structures fabricated in adjacent surface-adjoining semiconductor wells of the same conductivity type in a semiconductor substrate. The two LIGR structures are of generally similar configuration, thus simplifying the manufacturing process, and the proposed design additionally permits the n-channel and p-channel LIGR structures to have comparable "on" resistances. The two LIGR structures, otherwise isolated by a portion of the substrate separating the two semiconductor wells, are connected together by a common source electrode. The resulting complementary Lateral Insulated Gate Rectifier features a compact, integrated structure in which the "on" resistances of both the n-channel and p-channel portions of the device are comparable.
    Type: Grant
    Filed: December 22, 1986
    Date of Patent: December 8, 1987
    Assignee: North American Philips Corporation
    Inventor: Edward H. Stupp
  • Patent number: 4709255
    Abstract: A non-volatile storage cell has a floating conductive layer which is coupled to an injector region which is located in the semiconductor body and, viewed on the surface, is connected by a semiconductor zone entirely enclosed by a thick insulating layer to an electrode region of the storage transistor. The injector region is doped more weakly than the semiconductor zone and at least a part of the edge of the semiconductor zone follows in a self-registered manner an edge of the thick insulating layer. Furthermore, the floating conductive layer is located for at least half its size on the thick insulating layer.
    Type: Grant
    Filed: November 25, 1986
    Date of Patent: November 24, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Cornelius D. Hartgring, Johannes J. M. Joosten
  • Patent number: 4709163
    Abstract: A current-discrimination arrangement, in particular for use in stabilizing circuits, comprises two cross-coupled transistors. The current to be discriminated is applied in parallel to both transistors. For small currents both transistors conduct to the same extent, while at a current I=2(KT/qR), in which R is the resistance value of the collector load impedances of the two transistors, the circuit becomes bistable. The steep characteristic at the transition from non-stable to the bistable operation is used as discrimination characteristic.
    Type: Grant
    Filed: March 16, 1983
    Date of Patent: November 24, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Wolfdietrich G. Kasperkovitz
  • Patent number: 4707844
    Abstract: Charge-coupled devices are very sensitive to clock cross-talk due to the overlap between successive electrodes. The influence of this cross-talk is reduced when the clock lines are periodically connected to ground by a low-ohmic impedance. For this purpose, each clock line is controlled from a buffer, whose output is connected to a clock line. A clamping transistor is connected between the output and ground. When this clamping transistor is controlled by means of the output signal and at the same time by the input signal of the buffer, the output is clamped to ground at the instant at which the cross-talk is expected by means of only a single clamping transistor.
    Type: Grant
    Filed: June 18, 1986
    Date of Patent: November 17, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Hendrikus J. M. Veendrick, Adrianus T. Van Zanten, Leonardus C. M. G. Pfennings
  • Patent number: 4707719
    Abstract: The breakdown voltage of a p-n junction operated under reverse bias in at least one mode of operation of a semiconductor device is increased by providing at least one annular region forming an auxiliary p-n junction within the spread of a depletion layer from the reverse-biased junction. A passivating dielectric layer with an overlying electrically resistive layer extends over the semiconductor body surface between the active device region forming the p-n junction and a surrounding region of the body portion located beyond the (outer) annular region. The resistive layer is connected to these regions but is insulated from the annular regions by the dielectric layer. A stable high breakdown voltage can be obtained by providing the resistive layer with conductive connection means at the or each annular area which overlies the annular region(s).
    Type: Grant
    Filed: October 21, 1985
    Date of Patent: November 17, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Kenneth R. Whight
  • Patent number: 4697199
    Abstract: A semiconductor device has a safety device which includes an improved lateral bipolar transistor structure. The improvement is obtained by incorporating an auxiliary field effect transistor which has the emitter as its source zone and the collector as its drain zone, and in which the threshold voltage of the auxiliary field effect transistor is lower than the avalanche breakdown voltage of the collector-base junction of the lateral transistor. As a result, the lateral transistor switches sooner, at a lower voltage, to the readily conductive on-state.
    Type: Grant
    Filed: July 22, 1986
    Date of Patent: September 29, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Hendrik C. De Graaff, Wilhelmus G. Voncken