Abstract: An MOS integrated circuit arrangement with field-effect transistors includes a circuit arrangement for rapidly testing various blocks of the circuit. This circuit arrangement includes three transistor-switch groups; a first group for testing an input block, a second group for connecting and disconnecting the input block and an output block so that the blocks may be tested in combination, and a third group for testing the output block. The disclosed circuit provides a single and yet effective testing arrangement.

Abstract: A variable impedance circuit in which nonlinearities caused by the application of a signal are substantially reduced by the use of a feedback circuit for cancelling out the added input current due to the application of the input signal. By using a feedback circuit to obtain the desired improvement in linearity, the gain of the feedback loop can be tailored to obtain the necessary impedance range and output swing in a circuit capable of operating at relatively low power supply voltages.

Abstract: In order to improve yield, integrated circuits may advantageously be tested using internal test circuitry during fabrication to locate faults. In order to conduct the necessary tests without providing an extra external test connection, the invention contemplates using a required existing terminal of an integrated circuit along with a test circuit which is activated by a voltage outside the normal operating voltage range, such as a voltage of opposite polarity to that used during normal operation.

Abstract: A Class "B" amplifier circuit in which Class "B" conversion takes place in a converter portion of the circuit in combination with a differential amplifier input circuit, rather than in the output stage. The converter modulates the DC bias current supplied to the differential amplifier input circuit as a function of the input signal, in order to achieve Class "B" operation. The output amplifier portion of the circuit includes a pair of complementary, series-connected transistors, each of which is connected in a common-emitter configuration. The disclosed circuit provides a high input impedance and excellent dynamic range.

Abstract: A method of manufacturing a semiconductor device having at least one insulated gate field effect transistor in which a silicon body is provided with a silicon dioxide gate insulation layer and in which a boron-doped polysilicon electrode layer is formed on said layer, characterized in that the electrode layer is deposited by means of a low-pressure process, that the boron doping of the electrode layer is obtained by ion implantation, and that the silicon body is then subjected to a thermal treatment in an atmosphere containing hydrogen in which boron is diffused from the electrode layer through the gate insulation layer into a channel region underlying the electrode layer.

Abstract: A radiation-sensitive semiconductor device includes a radiation-detecting avalanche diode which has a semiconductor layer structure made up of four layers of the same type conductivity. The fourth semiconductor layer is located above the third layer and has a higher doping concentration than that of the third layer. This fourth layer substantially improves the noise properties of the device, by a factor of about 2. The radiation-sensitive semiconductor device is manufactured by a method in which the first and third layers of the semiconductor layer structure are provided by epitaxial growth, while the second and fourth layers of the structure are provided by ion implantation. The structure and method of the invention are particularly useful in the manufacture of avalanche photodiodes with an improved noise factor.

Abstract: A threshold arrangement includes two complementary transistors whose channels are situated in series between two supply terminals. In order to obtain a substantially square-wave relationship between the output voltage on the common drain electrodes and the input voltage on the interconnected gate electrodes, a direct voltage source is included between the two gate electrodes, which source has a voltage which is preferable substantially equal to the supply voltage minus the sum of the threshold voltages of the two complementary transistors.

Abstract: An injection laser includes two substantially parallel mirror side faces and a substantially stripe-shaped contact member having a comparatively large width. The stripe-shaped contact member has a shape and disposition with respect to the mirrors such that laser action can be obtained only in a comparatively narrow stripe of the active layer. For example, the contact member may be arranged to extend obliquely with respect to the mirrors instead of at right angles thereto.

Abstract: A memory cell for integration into a static memory includes two transistors with cross-coupled base and collector regions. The collector regions are connected to p-n junction diode load elements having at least one region of polycrystalline silicon material. The collector regions of the transistors are connected to the regions of the diodes which are of the same conductivity type as the collector regions.

Abstract: A Darlington transistor switch with a first and a second transistor, in which the base electrode of the first transistor is connected to the emitter electrode of the second transistor. In order to increase the switching speed of the device, the base-emitter capacitance of the second transistor relative to the base-emitter capacitance of the first transistor is increased so that voltage variations on the base of the second transistor with respect to the emitter of the first transistor are uniformly distributed over the base-emitter junctions of the two transistors.

Abstract: A multilayer power transistor includes an emitter zone having two layers of different doping levels, a less highly doped layer and a more highly doped surface region. The base zone of the transistor includes a central base region of higher doping level than that of the remainder of the base zone and which extends into the emitter surface region. This configuration results in a structure which exhibits a defocalization effect at any current level and improved secondary breakdown characteristics.

Abstract: A voltage clamping circuit for use in coupling line voltage signals to logic control circuitry used in domestic appliances includes a voltage dropping resistor coupled between input and output terminals. A first enhancement mode MOS transistor is coupled between a junction of the resistor and the output terminal and the V.sub.DD line. The gate of the first transistor is connected to the junction, so that when the voltage at the junction rises to a threshold voltage above V.sub.DD the first transistor is rendered conductive and clamps the positive line voltage cycle. A second enhancement mode MOS transistor is connected between the junction and the V.sub.DD line and its gate is connected to a biasing means which holds the second transistor nonconductive in response to the line voltage going negative until the junction is just above the V.sub.SS level, whereafter the second transistor turns on and clamps the input above V.sub.SS.

Abstract: A circuit for rapidly resynchronizing a clock with an external clock is disclosed. The clock to be synchronized is obtained at the output of a phase-locked loop by dividing the frequency of a reference clock in a frequency divider whose division factor is controlled by a phase controller which detects the deviation between the transitions of the two clocks to be synchronized. According to the invention, the pulses of the reference clock are applied to the phase-locked loop by means of a gate, with this gate being rendered nonconductive by means of the characteristic transition of the clock to be synchronized which follows the appearance of a resynchronizing control signal, and thereafter this gate is rendered conductive by means of a characteristic transition of the external clock.

Abstract: A gate turn-off PIN diode has its anode and cathode adjacent to the same major surface of the device body. The anode and cathode regions are separated by a recess which extends into the body towards the gate region. Turn-off is effected by the spread of a depletion layer from the reverse-biased gate junction to the recess.

Abstract: A method of manufacturing a semiconductor device having a multi-layer wiring system includes the steps of providing a first pattern of conductive regions on a major surface, providing an intermediate conductive layer over the major surface and the first pattern conductive regions, providing a second pattern of conductive tracks on the intermediate layer, and selectively etching the intermediate layer using the second pattern of tracks as an etching mask to completely remove the intermediate layer by underetching below portions of the second pattern tracks crossing over portions of the first pattern of conductive region where no electrical interconnection between the first and second conductive patterns is desired, while only partially removing the intermediate layer by underetching below portions of the second pattern of tracks crossing over portion of the first pattern of semiconductor regions where an electrical interconnection between the first and second conductor patterns is desired.

Abstract: A circuit arrangement for transferring a signal from a first A.C. circuit point to a second A.C. circuit point includes a resonant circuit and a current mirror. The input of the current mirror is connected to the resonant circuit, while its common emitter terminal is connected to the first A.C. circuit point and its output is connected to the second A.C. circuit point. In this manner one side of the resonant circuit may be grounded, even though the resonant circuit is effectively inserted between the two A.C. circuit points which are isolated from ground.

Abstract: A lateral double-diffused MOS transistor includes a field-shaping semiconductor layer which serves to improve the breakdown voltage and/or on-resistance characteristics of the device. The field-shaping layer redistributes the electrical field in the device during operation in order to eliminate electrical field crowding in portions of the device where breakdown would otherwise first occur. The field shaping layer may be a buried layer, a surface layer, or a composite layer having both buried and surface layer portions.

Abstract: A semiconductor injection laser includes two contact regions on two oppositely-located major surfaces of the semiconductor body. One of these contact regions is divided into two sub-contact regions which are separated by a gap, and the active zone of the laser can be moved in a direction transverse to that of the laser beam by controlling the current distribution between the two sub-contact regions in order to move the laser beam.

Abstract: A method of manufacturing a semiconductor device is disclosed in which a surface of a silicon body is provided successively with a silicon oxide layer and silicon nitride layer. Parts of the surface are exposed and are subjected to an oxidation treatment so as to obtain a sunken oxide pattern, during which treatment an undesired small silicon nitride strip or "white ribbon" is formed, and remaining parts of the silicon nitride layer and the underlying silicon oxide layer are then etched away. In the etching treatment, silicon nitride is etched more rapidly than silicon oxide and silicon, while silicon nitride is etched at approximately the same rate as silicon, so that the undesired "white ribbon" is removed.

Abstract: A constant current source circuit includes a single differential amplifier having both voltage and temperature stabilization circuits. The voltage and temperature stabilization circuits operate on a feedback principle, each receiving an input from the differential amplifier, and each in turn providing a signal back to the differential amplifier to provide the desired stabilization. The resulting circuit is particularly adapted for use in battery-powered equipment, where substantial variations in both temperature and operating voltage are likely to occur.