Abstract: The present invention relates to an oxidizing composition for treatment of keratin fibers comprising a combination of; (a) at least one anionic associative copolymer, (b) at least one anionic non associative copolymer; (c) at least one peroxide agent; (d) at least one persulfate agent; (e) at least on alkalizing agent; and (f) a carrier medium suitable for hair treatment. The oxidizing composition described is suitable for composition used in conventional hair treatments such as dyeing, bleaching, and permanent waving or relaxing/straightening of the keratinous fibers, particularly human hair, requiring an oxidizing composition.

Abstract: A fluid delivery system includes an applicator having gradient foam where the gradient foam includes a fluid and the applicator has an applicator surface area open to the environment such that the fluid is passively dispensed onto a surface independent of gravity through the applicator surface area. The gradient foam may be encompassed by a holder. A fluid reservoir in the applicator holder is used to replenish fluid. A cap covers the gradient foam to prevent the foam drying out. The types of surfaces that the fluid delivery system may be applied to can be hard or soft, such as wood or skin and hence, the fluid delivery system may be used for many applications in the home, health/medicine, beauty, feminine, baby, personal, fabric, pet and food areas.

Abstract: A package apparatus includes at least one memory chip, a voltage detection circuit configured to make a determination of whether a voltage supplied to the memory chip is a specific voltage or higher, and a controller configured to control an operation of the memory chip based on a result of the determination.

Abstract: A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.

Abstract: A semiconductor package includes a wire board, a plurality of semiconductor chips configured to be stacked over the wire board and to be electrically coupled with the wire board, and at least one shielding unit configured to be formed between the plurality of semiconductor chips and to be maintained at a predetermined voltage.

Abstract: A writing utensil kit comprising a plurality of writing utensils including an associated tip having at least one notch formed therein and adapted to mechanically engage a writing surface and produce a stylized design when manipulated thereupon by a user. A method of using the writing utensil wherein a user selects a writing utensil from the kit; orients the writing utensil such that the writing utensil is in mechanical engagement and fluid communication with a writing surface; and manipulates the writing utensil such that a stylized design is produced thereupon.

Abstract: A system and method for dynamically recognizing a potential recipient of an electronic message. The method includes receiving content input for an electronic communication. The electronic communication includes at least one field of a plurality of fields, including a subject line, a message body, and a recipient address field. The at least one field of the electronic communication is populated with the content input. The method also includes parsing the content input of the at least one field of the electronic communication. The method also includes semantically analyzing the parsed content input of the at least one field of the electronic communication to identify a content qualifier of a recipient rule. The method also includes suggesting a potential recipient of the electronic communication based on the content qualifier of the recipient rule associated with the content input of the at least one of field of the electronic communication.

Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

Abstract: A double-helix spiral conveyor, a method for conveying articles up and down a spiral conveyor, and a method for constructing a drive drum for a spiral conveyor. The double-helix spiral conveyor conveys articles on the conveyor up the inner side of a spiral drum by engaging the outer edge of the belt and down the outer side of the drum by engaging the inner edge of the belt. A slew drive at the bottom of the drum drives the conveyor.

Abstract: A primary aluminum hydride cell and a battery formed with a plurality of the cells is described herein. The cells are constructed of an anode, a cathode and an aqueous electrolyte, and the anode comprises aluminum hydride and a conductive material. In some embodiments, the cathode comprises an air diffusion cathode.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A fuse layout structure of a semiconductor device includes a plurality of fuses in a fuse open area, wherein three neighboring fuses of the plurality of fuses form a fuse unit, and at least one of the fuses partially overlaps at least one of the other fuses of the same fuse unit in the fuse open area.

Abstract: A nonvolatile memory device includes a data latch unit configured to store data to be programmed into a memory cell or store data read from a memory cell, and page buffers each comprising a sense node discharge unit configured to selectively ground a sense node depending on data stored in the data latch unit and in response to a sense node discharge signal.

Abstract: Provided are methods for determining the activity of proteins that modulate the acetylation state of a protein substrate. The methods may be used for determining both acetyltransferase activity and deacetylase activity. The methods utilize mass spectrometry for determining the acetylation state of a substrate peptide. The methods may also be used to identify compounds that modulate the activity of a protein having acetyltransferase or deacetylase activity. In some embodiments, a compound that modulates a deacetylase is an activator of the deacetylase.

Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

Abstract: A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.