Abstract: A method of fabricating a contact pad of a semiconductor device is disclosed. The method includes forming a stopping layer over the semiconductor substrate. An interdielectric layer is formed over the stopping layer, and the interdielectric layer is planarized to expose at least a gate upper dielectric layer by using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer. The interdielectric layer is etched in a region in which a contact pad will be formed on the semiconductor substrate. A conductive material is deposited on the semiconductor substrate. Finally, planarizing is carried out using a material which exhibits a high-polishing selectivity of the upper dielectric layer with respect to the conductive material.

Abstract: An airflow damper is affixed to a top interior wall of a hard disk assembly, so that a specified gap distance between the airflow damper and an upper disk within the hard disk assembly is realized. The gap distance is determined as a function of velocity of the driven disks. The airflow damper is designed to have a thickness so that the determined gap distance is realized for the given velocity. The airflow damper eliminates secondary airflow within the hard disk assembly, to prevent formation of a large vortex above the upper disk and to thus reduce airborne noise.

Abstract: A method of fabricating a semiconductor apparatus includes forming a base member and a conductive layer on a first surface of a semiconductor substrate. The conductive layer has an extended portion that extends onto the base member. A first surface of the semiconductor substrate is placed to face a connection substrate, the extended portion of the conductive layer is then connected to the connection substrate, and a seal member is supplied in a space between the semiconductor substrate and the connection substrate.

Abstract: A gate electrode layer formed on a semiconductor substrate is etched. A gate electrode is formed while forming metal system sub-products onto the side walls of the gate electrode layer. The metal system sub-products formed on the side walls of the gate electrode layer are oxidized. The oxidized metal system sub-products are removed by a solution whose etching rate for the gate insulative film has been adjusted to 10 Å/min or less.

Abstract: A semiconductor device comprises an SAC structure having side wall spacers and offset nitride films. In particular, in this semiconductor device, the side wall spacers are constituted from lower side wall spacers that are composed of silicon oxide films and are in contact with the lower side of the gate electrode side walls, and upper side wall spacers that are composed of silicon nitride films and are in contact with the upper side of the gate electrodes side walls. As a result thereof, a distance is formed between the substrate and the interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurrence of poor contact.

Abstract: A temperature sensor device for use in a clean room has a housing, a covering tube extending from the housing, a lead wire protecting tube extending from the housing within the covering tube, and a generally cylindrical temperature sensor also disposed within the covering tube. A fixing end of the temperature sensor is detachably coupled to a distal end of the lead wire protecting tube. A plurality of lead wires protrude from the fixing end and extend through the lead wire protecting tube and into the housing. The temperature sensor includes a temperature sensor element at a free end thereof. The covering tube has at least one hole by which the temperature sensor element is exposed to the atmosphere. Accordingly, the temperature sensor is highly responsive to changes in temperature, and can be repaired, maintained or replaced with ease.

Abstract: An operational amplifier includes: a differential input section for generating a first signal corresponding to a differential voltage between two input signals; an amplifying section for amplifying the first signal in voltage to generate second and third complementary signals; a first MOS transistor connected between a first supply voltage and an output node, a conduction state of the first MOS transistor being controlled in accordance with the second signal; a second MOS transistor connected between a second supply voltage and the output node, a conduction state of the second MOS transistor being controlled in accordance with the third signal; and a step-up section for stepping up the first and second supply voltages to generate a step-up voltage higher than the first and second supply voltages; wherein the amplifying section is driven by the step-up voltage so that absolute value of the maximum level of the second or third signal becomes larger than the absolute value of the first or second supply voltage.

Abstract: An operating condition of an operating circuit is provided to a register, a counter is set in accordance with an operating condition signal stored in the register, and the counter outputs a reset signal to the operating circuit. The operating condition signal indicates a reset delay period which is equal to the sum of a shortest rise time of power supply voltage and a reset period to reset the counter after the power supply voltage has settled.

Abstract: A resist removing composition having a superior capability for removing a resist, polymer, organometallic polymer and etching by-products such as metal oxide, which does not attack underlying layers exposed to the composition and which does not leave residues after a rinsing step. The resist removing composition contains alkoxy N-hydroxyalkyl alkanamide and a swelling agent.

Abstract: A sputter apparatus (10) includes a chamber (13a) housing a target (11), a work piece support (12) and a process area (14) between the target and the support. The apparatus further includes an inlet (24) for process gas and a pumping outlet (27) from the process area. The inlet substantially surrounds the support and the apparatus includes a pumping outlet separate from the inlet. The inlet is shielded from the process area.

Abstract: The present invention provides a compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations. In the electrostatic-breakdown-preventive and protective circuit for a semiconductor-device of the invention, a protective transistor is provided between a power-source line and a ground line for an input/output circuit, a position between a power-source line and ground line for a circuit block A, a position between a power-source line and a ground line for a circuit block B, and a position between a power-source line and a ground line for an input/output circuit. A PMOS protective transistor is provided between the power-source line for the circuit block A and the power-source line for the circuit block B, and an NMOS protective transistor is provided between the ground lines in an internal-circuit region in the vicinity of a signal line (protective resistor).

Abstract: A vertical type chemical vapor deposition apparatus includes a process chamber having a cylindrical inner tube and a cap shaped outer tube surrounding and apart from the inner tube. A manifold is coupled with lower portions of the inner and outer tubes, and has a lower portion tapered at an inclination angle. A heater is provided at an outer side of the outer tube for heating the process chamber. A boat is movable into and out of the process chamber through the manifold, as driven by an elevator. The boat is vertically loaded with wafers. A cap is fixed to the elevator at a lower portion of the boat, and has a portion contactable with the manifold that is tapered at a same inclination angle as the lower portion of the manifold. An O-ring is inserted into the portion of the cap contactable with the manifold.

Abstract: In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side wall of the silicon nitride film is formed in an opening in the P type poly-crystal silicon layer above a portion expected to provide an active region. The first silicon oxide film has an opening therein which is larger than the opening formed in the P type poly-crystal silicon layer. Then, an N type IV-group semiconductor mixed crystal layer having a smaller band gap than silicon to a desired thickness is grown on the single-crystal silicon substrate on which a surface of the portion expected to provide said active region is exposed. A non-doped single-crystal silicon layer is grown on the IV-group semiconductor mixed crystal layer to a desired thickness.

Abstract: A plurality of posts 12 having electrical conductivity are formed on a side of a plate member 11. A buffer layer 14 is formed on the side of the plate member 11 so that top ends of the posts 12 are protruded from the buffer layer 14. The semiconductor pellet 17 is mounted on a predetermined position on the top ends of the posts 12. The electrodes of the semiconductor pellet 17 are connected to the top ends of the posts 12 by means of wires 18. A resin portion 20 is formed on the buffer layer 14 so that the resin portion 20 encapsulates the posts 12, the wires 18 and the semiconductor pellet 17. The plate member 11 is removed from the buffer layer 14 and the posts 12, so that the posts 12 are electrically separated from each other. Solder balls 23 are bonded to the bottom ends 21 of the posts 12.

Abstract: A first IC chip having an electrode pad to which a re-wiring layer is not connected and a second IC chip having an electrode pad to which the re-wiring layer is connected are electrically connected to each other via a conductor post formed on the electrode pad on the first IC chip, thereby electrically connecting and integrating the first and second IC chips.

Abstract: A semiconductor device has a field-effect transistor with a source, drain, and channel formed in an active region surrounded by a field region. The boundary between the channel region and field region includes crenellations that reduce the effect of contaminating particles and defects. The crenellated boundary can be formed by polysilicon-buffered local oxidation of silicon, or by use of a crenellated mask pattern.

Abstract: A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n−1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read out from each dummy memory cell, a potential Va is developed on a bit line BL2n−1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n−1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn−1 and SAn as a reference potential.

Abstract: In an opto-electronic module including an opto-electronic unit and a receptacle, the receptacle has an outer indentation. When the module is assembled, the receptacle is held in a fixture with a projecting lip that fits into the indentation. After optical alignment, the receptacle is fastened to the opto-electronic unit by welding. The projecting lip prevents the receptacle from moving during the welding process, thereby assuring that optical alignment is maintained.

Abstract: An input receiver controls an offset voltage by using an output feedback signal to improve a sense speed. The input receiver includes a pre-amplifier that controls an offset voltage in response to a feedback signal and amplifies an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal. Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.

Abstract: An apparatus for use in orienting an object at a reference angle includes a pin gauge having at least two projections located at an end of the body of the apparatus. The projections are located at certain X Y coordinates of an X, Y Z Cartesian coordinate system. A horizontal support supports the body so as to be movable horizontally in the longitudinal direction of the projections. A mechanical drive member is operable to move the body mechanically in the horizontal direction. The apparatus may also include a vertical support and vertical drive member. The pin gauge is mechanically moved into contact with a surface of an object to provide a reference angle for the object. Then the object is pivoted, if necessary, to bring the surface into point contact with all of the projections of the pin gauge, whereupon the object is oriented at the reference angle.