Abstract: A semiconductor structure includes a substrate and a semiconductor devices secured to the substrate. A stabilizing member is secured to the semiconductor device, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the substrate. The bending stiffness of the substrate is substantially the same as the bending stiffness of the stabilizing member, wherein: bending stiffness=Et3, with E=Young's modulus, and t=thickness. In another embodiment, a stabilizing member is secured to the substrate, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the die. The bending stiffness of the die is substantially the same as the bending stiffness of the stabilizing member, with bending stiffness defined as above.

Abstract: A method is provided for a process control based on tool health data. The method comprises processing a workpiece using a processing tool, receiving trace data associated with the processing of the workpiece from the processing tool and determining at least one value associated with a health of a portion of the processing tool based on at least a portion of the received trace data. The method further comprises adjusting processing of another workpiece based on the determined health value.

Abstract: A test structure includes a plurality of lines and a plurality of contact openings defined in the lines. A method for determining contact opening dimensions includes providing a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines; illuminating at least a portion of the contact openings with a light source; measuring light reflected from the illuminated portion of the contact openings to generate a reflection profile; and determining a dimension of the contact openings based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the contact openings. The detector is adapted to measure light reflected from the illuminated portion of the contact openings to generate a reflection profile.

Abstract: There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.

Abstract: A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.

Abstract: The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices.

Abstract: A microprocessor configured to store victimized instruction and data bytes is disclosed. In one embodiment, the microprocessor includes a predecode unit, and instruction cache, a data cache, and a level two cache. The predecode unit receives instruction bytes and generates corresponding predecode information that is stored in the instruction cache with the instruction bytes. The data cache receives and stores data bytes. The level two cache is configured to receive and store victimized instruction bytes from the instruction cache along with parity information and predecode information, and victimized data bytes from the data cache along with error correction code bits. Indicator bits may be stored on a cache line basis to indicate the type of data is stored therein.

Abstract: A highly integrated multimedia processor employs a shared cache between tightly coupled central processing and graphics units to provide the graphics unit access to data retrieved from system memory or data processed by the central processing unit before the data is written-back or written-through to system memory, thus reducing system memory bandwidth requirements. Regions in the shared cache can also be selectively locked down thereby disabling eviction or invalidation of a selected region, to provide the graphics unit with a local scratchpad area for applications such as, but not limited to, temporary video line buffering storage for filter applications and composite buffering for blending texture maps in multi-pass rendering.

Abstract: The present invention is generally directed to various methods of controlling copper barrier/seed deposition processes, and a system for accomplishing same. In one illustrative embodiment, the method comprises performing at least one process operation to form a barrier metal layer and a copper seed layer above a wafer, sensing at least one parameter of at least one process operation and determining an acceptability metric for the barrier metal layer and the copper seed layer based upon the sensed at least one parameter. In some embodiments, the method further comprises modifying at least one parameter of said at least one process operation to be performed to form a barrier metal layer and a copper seed layer on a subsequently processed wafer based upon said determined acceptability metric. In some embodiments, the method further comprises identifying a wafer as unacceptable if said acceptability metric falls below a preselected level.

Abstract: A method for scheduling a resource for processing a workpiece includes defining a commitment window having a kernel specifying a time period required for processing the workpiece. A plurality of candidate bids having candidate commitment windows within the commitment window with varying start times, end times and candidate commitment window sizes is generated. A cost for each of the plurality of candidate bids is determined. A flexibility discount is applied to the cost of the candidate bid. Each candidate bid is evaluated in accordance with an objective function. A candidate bid is selected for scheduling the resource based on the objective function evaluation. A system includes a resource for processing a workpiece and at least one scheduling agent.

Abstract: The present invention provides for a method and an apparatus for implementing a control simulation environment into a manufacturing environment. A process task is defined. A process simulation function is performed to produce simulation data corresponding to the process task. The simulation data is integrated with a process control environment for controlling a manufacturing process of a semiconductor device.

Abstract: An Audio Encoder/Decoder (AC)-97 protocol link is used for concurrent data communication between AC-97 protocol devices and non-AC-97 protocol devices. The Tag data in an AC-97 data frame is used to select specific CODECs and to determine which data time slots to ignore or accept. Since telephone voice and data communication uses only the Tag data and one other of the data frame time slots, eleven slots are available for communication using non-AC-97 protocol devices concurrent with telephony communications. Ethernet, Home Phoneline Network Alliance (HPNA), Attachment Unit Interface (AUI) are some of the data communication protocols that may be employed using embodiments of the present invention. An AC-97 data communication controller may modified with additional logic and control lines to support additional features of non-AC-97 protocol devices.

Abstract: An asymmetric double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a first fin formed on a substrate; a second fin formed on the substrate; a first gate formed adjacent first sides of the first and second fins, the first gate being doped with a first type of impurity; and a second gate formed between second sides of the first and second fins, the second gate being doped with a second type of impurity. An asymmetric all-around gate MOSFET includes multiple fins; a first gate structure doped with a first type of impurity and formed adjacent a first side of one of the fins; a second gate structure doped with the first type of impurity and formed adjacent a first side of another one of the fins; a third gate structure doped with a second type of impurity and formed between two of the fins; and a fourth gate structure formed at least partially beneath one or more of the fins.

Abstract: A processor includes an integer unit operable to execute integer instructions and a floating point unit operable to execute floating point instructions. The processor also includes at least one spare fill cell disposed in at least one portion of the processor that is not occupied by the integer unit and the floating point unit. The at least one spare fill cell includes at least one spare transistor configured as a capacitor and coupled to a voltage rail and a ground rail.

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract: A method for controlling a manufacturing system includes processing workpieces in a plurality of tools; initiating a baseline control script for a selected tool of the plurality of tools; providing context information for the baseline control script; determining a tool type based on the context information; selecting a group of control routines for the selected tool based on the tool type; determining required control routines from the group of control routines based on the context information; and executing the required control routines to generate control actions for the selected tool. A manufacturing system includes a plurality of tools adapted to process workpieces, a control execution manager, and a control executor. The control execution manager is adapted to initiate a baseline control script for a selected tool of the plurality of tools and provide context information for the baseline control script.

Abstract: A MOS ring oscillator includes a number of serially connected inverter stages with each stage comprising a MOS transistor pair. At least one of the transistors also comprises a scatterometry grate array, which is used during manufacturing of the ring oscillator to obtain scatterometry measurements that allow polysilicon lines of the MOS ring oscillator to have widths of less than 60 nm. A method includes forming at least one grate array above a substrate, illuminating the grate array, measuring light reflected off of the grate array to generate an optical characteristic trace for the grate array, and comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a grate array having a desired profile.

Abstract: The present invention is generally directed to various methods of controlling wafer charging effects due to manufacturing processes, and a system for performing same. In one illustrative embodiment, the method comprises identifying a process metric associated with a process operation that is capable of generating a charge that is stored in at least one of a process layer and a feature formed above a substrate. In other embodiments, the method involves establishing a metric for a plasma-based process operation. The methods include establishing an allowable range for the process metric based upon data obtained from at least one electrical test performed on at least one semiconductor device subjected to the process operation, performing the process operation and indicating an alarm condition if the process metric associated with the process operation is not within the allowable range.

Abstract: Various embodiments of a semiconductor-on-insulator substrate incorporating a Peltier effect heat transfer device and methods of fabricating the same are provided. In one aspect, a circuit device is provided that includes an insulating substrate, a semiconductor structure positioned on the insulating substrate and a Peltier effect heat transfer device coupled to the insulating substrate to transfer heat between the semiconductor structure and the insulating substrate.

Abstract: In one embodiment, a process for fabricating a high-K layer comprising the steps of: placing a semiconductor substrate into a first chamber of a deposition apparatus; supplying high-K precursors to the deposition apparatus; generating ions or molecules of high-K material from the high-K precursors in a second chamber of the deposition apparatus, the second chamber being remote from the first chamber; passing the ions or molecules of high-K material from the second chamber to the first chamber; and depositing a high-K layer upon the semiconductor substrate.