Abstract: A technique for configuring a computing system that allows for multiple computing systems and device populations to be supported by a single BIOS implementation is presented. In one embodiment, the technique includes processing topology map parameters that describe physical connections of a computing system, wherein the computing system includes a plurality of processing nodes; determining routing paths for traffic between the plurality of processing nodes; and determining a population of the plurality of processing nodes. In one embodiment, the determining the routing paths is performed during BIOS build time. In another embodiment, the determining the routing paths is performed during BIOS run time.

Abstract: A technique in which a first boundary region is added to the ends of phase zero (0) pattern defining polygons and a second boundary region is added to the ends of phase 180 pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.

Abstract: Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing.

Abstract: An interface circuit is disclosed for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, where the phase and frequency relationships of the first and second clock signals are known. The interface circuit comprises: 1) a flip-flop having a data input for receiving a first data signal from the first clock domain, a clock input for receiving the first clock signal, and an output; 2) a latch having a data input coupled to the flip-flop output, a clock input for receiving a gating signal, and an output; and 3) a multiplexer having a first data input coupled to the flip-flop output, a second data input coupled to the latch output, and a selector input for selecting one of the first and second data inputs for the multiplexer output.

Abstract: A graphics subsystem including a RAMDAC for connection to a graphics bus implemented on an integrated circuit chip separate from a graphics processor. In one embodiment, the graphics processor is configured to render digital image information in response to graphics commands and to store the digital image information in a memory. The RAMDAC IC includes a conversion unit, which includes a color mapping unit and a digital-to-analog converter and is configured to convert a representation of the digital image information into one or more analog signals for driving a video display. The graphics subsystem further includes a Direct Memory Access (DMA) controller implemented on the second integrated circuit chip. The DMA controller is configured to generate read requests to retrieve the digital image information stored in the memory to thereby cause the digital image information to be provided to the conversion unit.

Abstract: Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.

Abstract: One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.

Abstract: A dual gate semiconductor device, such as a flash memory semiconductor device, whose plurality of dual gate sidewall spacer structure is formed by a first and second anti-reflection fabrication process. The sidewall spacers of the dual transistor gate structures in the core memory region are left coated with the second anti-reflective coating material, after being used for gate patterning, to act as sidewall spacers for use in subsequent ion implant and salicidation fabrication steps. The second anti-reflective coating material is selected from a material group such as silicon oxynitride (SiON), silicon nitride (Si3N4), and silicon germanium (SiGe), or other anti-reflective coating material having optical properties and that are compatible with the subsequent implant and salicidation steps.

Abstract: According to one exemplary embodiment, a method for forming a field effect transistor over a substrate comprises a step of forming an interfacial oxide layer over a channel region of the substrate, where the interfacial oxide layer has a first thickness. The interfacial oxide layer can prevent a high-k element from diffusing into the channel region. The method further comprises forming an oxygen-attracting layer over the interfacial oxide layer, where the oxygen-attracting layer prevents the first thickness of the interfacial oxide layer from increasing. The oxygen-attracting layer is formed by forming a metal layer over the interfacial oxide layer, where the metal layer combines with oxygen to form a silicate. The oxygen-attracting layer may be zirconium silicate or hafnium silicate, for example. The method further comprises forming a high-k dielectric layer over the oxygen-attracting layer. The method further comprises forming a gate electrode layer over the high-k dielectric layer.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a policy filter configured for obtaining layer 3 and layer 4 information from a received layer 2 frame. The layer 3 information and the layer 4 information is used to determine a policy identifier that specifies a layer 3 switching operation to be performed on the received layer 2 frame. Each network switch port also includes a flow identification module that caches portions of the layer 3 information and the corresponding policy identifier.

Abstract: A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.

Abstract: A system and methodology are disclosed for forming a passive layer on a conductive layer. The formation can be done during fabrication of an organic memory cell, where the passive layer generally includes a conductivity facilitating compound, such as copper sulfide (Cu2S). The conductivity facilitating compound is deposited onto the conductive layer via plasma enhanced chemical vapor deposition (PECVD) utilizing a metal organic (MO) precursor. The precursor facilitates depositing the conductivity facilitating compound in the absence of toxic hydrogen sulfide (H2S), and at a relatively low temperature and pressure (e.g., between about 400 to 600 K and 0.05 to 0.5 Pa., respectively). The deposition process can be monitored and controlled to facilitate, among other things, depositing the conductivity facilitating compound to a desired thickness.

Abstract: A process of siliciding uses alloys to reduce the adverse affects of germanium on silicide regions. The alloy can include nickel and at least one of vanadium, tantalum, and tungsten. The process can utilize one or two annealing steps. The process allows better silicidation in SMOS devices. The silicided regions can be provided above a silicon/germanium substrate.

Abstract: A method of manufacturing a metal layer structure and a corresponding integrated circuit chip are provided, wherein the integrated circuit chip comprises metal layers and via holes. The via holes electrically connect a metal line of one metal layer with a metal line of another metal layer. The metal lines and via holes form a signal path that electrically connects a first tap with a second tap. The metal lines in each metal layer are arranged in a first predefined configuration. There is for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with a third tap. This technique is particularly useful for storing revision identification data.

Abstract: Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.

Abstract: A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is employed to determine an average dynamic reference value. The average dynamic reference value is determined by reading a programmed bit of the first reference cell and reading an unprogrammed or erased bit of a second reference cell to determine an average dynamic reference value. The average dynamic reference value can be utilized to determine whether data cells are in a programmed state or in an unprogrammed state.

Abstract: A wedge-shaped nozzle for dispensing fluids onto a round surface is disclosed. The nozzle dispenses the fluid with a generally uniform volume of fluid per unit area of the round surface to achieve rapidly a uniform thickness of applied fluid on the round surface. The wedge-shaped nozzle has orifices of equal size disposed on its bottom through which the fluid is dispensed. The orifices are disposed along arcs, with increasing numbers of orifices on the arcs at greater and greater distances of the arcs from the apex of the wedge-shaped nozzle. The numbers of the orifices on each arc are proportional to the area of an annular region determined by the arcs.

Abstract: A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.

Abstract: A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

Abstract: A method and an apparatus for performing a batch organization of semiconductor wafers. Data relating to metrology data associated with a processed semiconductor wafer in a lot is acquired. A quality characteristic associated with the processed semiconductor wafer is determined based upon the metrology data. A plurality of semiconductor wafers associated with the lot re-organized for subsequent processing, based upon the quality characteristic.