Abstract: A process for improving the accuracy of critical dimension measurements of features patterned on a photoresist layer using a scanning electron microscope (SEM) is disclosed herein. The process includes providing an electron beam to the photoresist layer and transforming the surface of the photoresist layer before the SEM inspection. The surface of the photoresist layer is transformed to trap the outgassing volatile species and dissipates built up charge in the photoresist layer, resulting in SEM images without poor image contrast.

Abstract: A method includes providing a wafer having a first grating structure and a second grating structure formed in a photoresist layer. At least a portion of the first and second grating structures is illuminated with a light source. Light reflected from the illuminated portion of the first and second grating structures is measured to generate a reflection profile. Misregistration between the first and second grating structures is determined based on the reflection profile. A processing line includes a photolithography stepper, a metrology tool, and a controller. The photolithography stepper is adapted to process wafers in accordance with an operating recipe. The metrology tool is adapted to receive a wafer processed in the stepper. The wafer has a first grating structure and a second grating structure formed in a photoresist layer. The metrology tool includes a light source, a detector, and a data processing unit.

Abstract: A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.

Abstract: Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a polysilicon gate structure while source/drain regions are covered. A second phase conductive metal silicide is formed consuming substantially all of the polysilicon and providing a substantially uniform work function at the silicide/gate oxide interface.

Abstract: In a packet switch, such as an Ethernet switch, the network interface cards (NICs) of the switch perform processing functions relating to tags that identify packets or frames for a particular virtual local area network (VLAN) supported by the switch. Descriptors used to process the frames in the buffer memory of the switch provide tag information and tag status indicators and/or tag processing commands. Upon reception of a frame, a NIC recognizes the type of the frame as it relates to VLAN tagging. As the NIC writes the frame to a receive buffer location, it also writes a tag type indicator and any tag information read from the frame into the receive descriptor for that frame. The switch CPU creates a transmit descriptor that includes the pointer to the transmit buffer location in memory, and that descriptor includes a tag control command as well as a tag information field.

Abstract: A system for detecting voids in an ILD layer is provided. The system includes one or more light sources, each light source directing light to respective portions of the ILD layer. Light reflected from the respective portions is collected by a measuring system that processes the collected light. The collected light is indicative of the presence of voids in the respective portions of the ILD layer. The measuring system provides ILD layer void related data to a processor that determines whether voids exist in the respective portions of the ILD layer. The processor selectively marks the ILD layer portions to facilitate further processing and/or destruction of the IC with the ILD layer voids.

Abstract: A novel method of enabling a port of a network switch to support connections with multiple VLANs. The method comprises storing VLAN data indicating a plurality of VLAN identifiers corresponding to the multiple VLANs supported by the port. A VLAN identifier of a data packet received via the port is compared with the plurality of VLAN identifiers determined using the stored VLAN data. The data packet is forwarded for further processing if the VLAN identifier matches one of the plurality of VLAN identifiers. However, the data packet is discarded if the VLAN identifier does not match one of the plurality of VLAN identifiers. Moreover, VLAN information corresponding to a VLAN identifier of a data packet to be transmitted from the port is compared with the stored VLAN data to determine whether the VLAN identifier matches one of the plurality of VLAN identifiers supported by the port.

Abstract: A semiconductor-on-insulator (SOI) device. The SOi device includes a substrate, an insulator layer disposed on the substrate and an active region disposed on the insulator layer. The active region includes a source, a drain, and a body disposed therebetween. The source and body form an abrupt or hyperabrupt source/body junction. A gate is disposed on the body to operatively form a transistor. An implanted region forms an interface between the body and the drain, the implanted region formed by tilted atom implantation in a direction towards the active region and under the gate from an angle tilted towards the drain with respect to vertical, the implanted region resulting in the formation of a graded drain/body junction. Also disclosed is a method of fabricating the SOI device.

Abstract: In a method of in situ controlling the degree of fullness of wide lines in a damascene structure, an optical endpoint detection signal is analyzed so as to determine a time interval of substantially constant signal amplitude. The time interval is then used as a measure of the metal filled in a wide line in a damascene structure. By correlating the length of the time interval to at least one process parameter involved in the formation of the damascene structure, the degree of fullness of lines in the damascene structure may be controlled to maintain within a predefined allowable range.

Abstract: A method and an apparatus for dynamic targeting for a process control system. A process step is performed upon a first workpiece in a batch based upon a process target setting. The process target setting comprises at least one parameter relating to a target characteristic of the first workpiece. Manufacturing data relating to processing of the first workpiece is acquired. The manufacturing data comprises at least one of a metrology data relating to the processed first workpiece and a tool state data relating to the tool state of a processing tool. Electrical data relating to the processed first workpiece is acquired at least partially during processing of a second workpiece in the batch. The process target setting is adjusted dynamically based upon a correlation of the electrical data with the manufacturing data.

Abstract: According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

Abstract: A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

Abstract: A method for generating a memory of various sizes and configurations uses a plurality of banks. The banks are selected to meet memory requirements and size constraints and are arranged in an orthogonal array. Critical paths are minimized using commercially available software.

Abstract: A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in response, to send a probe to determine whether any of the other caches contain a copy of the requested data. Some time after sending the probe, the cache controller may provide a speculative response to the cache fill request to the requesting device. By delaying providing the speculative response until some time after the probes are sent, it may become more likely that the responses to the probes will be received in time to validate the speculative response.

Abstract: A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.

Abstract: Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.

Abstract: Methods are described for characterizing floating body delay effects in SOI wafers comprising providing a pulse edge to a floating body and a tied body chain in the wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects according to the stored tied body chain data. Test apparatus are also described comprising a floating body chain including a plurality of series connected floating body inverters or NAND gates fabricated in the wafer and a tied body chain comprising a plurality of series connected tied body devices to in the wafer. Storage devices are coupled with the tied body devices and with one or more of the floating body devices and operate to store tied body chain data from the tied body devices according to one or more signals from floating body chain.

Abstract: The present invention provides a low-k dielectric constant structure and method of forming the same on a substrate 10 that features having a dielectric layer 20 with differing regions of density 12 and 18. To that end, the method includes depositing, upon the substrate, a dielectric layer having first and second density regions. The density associated with the second density region being greater than the density associated with the first density region, and the first density region being disposed between the substrate and the second density region.

Abstract: A method for determining critical dimension variation includes providing a wafer having a grating structure comprising a plurality of lines; illuminating at least a portion of the lines with a light source; measuring light reflected from the illuminated portion of the lines to generate a reflection profile; and determining a critical dimension variation measurement of the lines based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure comprising a plurality of lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the lines. The detector is adapted to measure light reflected from the illuminated portion of the lines to generate a reflection profile. The data processing unit is adapted to determine a critical dimension variation measurement of the lines based on the reflection profile.

Abstract: A core voltage for a core logic region of an integrated circuit is specified by a programmable register on the integrated circuit. Output terminals on the integrated circuit are coupled to the programmable storage location and supply voltage control signals for a voltage regulator to specify the core voltage according to the contents of the programmable register. The output terminals may output a programmable voltage setting or a fixed voltage setting that specifies a default core voltage value, depending on reset conditions.