Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.
Type:
Grant
Filed:
December 2, 2002
Date of Patent:
September 7, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Yi He, Edward F. Runnion, Zhizheng Liu, Mark W. Randolph, Darlene G. Hamilton, Pauling Chen, Binh Le
Abstract: The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors.
Abstract: A method of manufacturing an integrated circuit utilizes a thin film substrate. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.
Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.
Type:
Grant
Filed:
December 31, 2002
Date of Patent:
September 7, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Eric N. Paton, Qi Xiang, Paul R. Besser, Ming-Ren Lin, Minh V. Ngo, Haihong Wang
Abstract: A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.
Type:
Grant
Filed:
March 12, 2003
Date of Patent:
September 7, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Chih-Yuh Yang, Shibly S. Ahmed, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Bin Yu
Abstract: High-speed semiconductor devices with reduced source/drain junction capacitance and reduced junction leakage based on strain silicon technology are fabricated by extending a shallow trench isolation region under the strained silicon layer. Embodiments include anisotropically etching the trench region and subsequently isotropically etching the trench to form laterally extending regions under the strained silicon layer. Embodiments also include filling the trench with an insulating material such that an air pocket is formed in the trench.
Abstract: One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
Type:
Grant
Filed:
July 7, 2003
Date of Patent:
September 7, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Nicholas H. Tripsas, Matthew S. Buynoski, Suzette K. Pangrle, Uzodinma Okoroanyanwu, Angela T. Hui, Christopher F. Lyons, Ramkumar Subramanian, Sergey D. Lopatin, Minh Van Ngo, Ashok M. Khathuria, Mark S. Chang, Patrick K. Cheung, Jane V. Oglesby
Abstract: A double-gate vertical MOSFET transistor is described along with an associated fabrication method. The MOSFET transistor is configured with separate gates on each side of a vertical source-drain channel that is capped by an insulation layer. The fabrication process generally comprises forming a silicon-insulator stack having a silicon fin (channel) capped with insulation. The opposing ends of the silicon-insulator stack being configured with areas capable of receiving source and drain contacts. The vertical surfaces of the silicon fin are insulated prior to the formation of gate electrodes adjacent the two opposing sides of the silicon-insulator stack. By way of example, the gate electrodes are formed by depositing a thick layer of conductive gate material over the substrate and then removing the adjoining upper portion, such as by polishing. Portions of each gate electrode are configured with areas capable of receiving a gate contact.
Abstract: A domain power notification system detects when a power domain experiences a power condition, such as lost power and low-voltage power, and communicates that information to the domains that communicate with the problem domain. As a result, the effected domains stop communicating with the problem domain without passing erroneous information.
Abstract: A method is provided for compressing data. The method comprises collecting processing data representative of a process. The method further comprises modeling the collected processing data using a control model. The method also comprises applying the control model to compress the collected processing data.
Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.
Type:
Grant
Filed:
November 8, 2002
Date of Patent:
September 7, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Shibly S. Ahmed, Cyrus E. Tabery, Haihong Wang, Bin Yu
Abstract: A method and an apparatus for acquiring pre-process and post-process integrated metrology data. A lot of semiconductor wafers is provided. A pre-process integrated metrology data acquisition from a first semiconductor wafer within the lot of semiconductor wafers is performed. A process operation on the first semiconductor wafer is performed at least partially during the process of acquiring pre-process metrology data from a second semiconductor wafer within the lot of semiconductor wafers. Post-process integrated metrology data is acquired from the first semiconductor wafer in response to processing of the first semiconductor wafer. The pre-process and the post-process metrology data is analyzed for evaluation of the process operation performed on the first semiconductor wafer.
Type:
Grant
Filed:
December 17, 2001
Date of Patent:
September 7, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Alexander J. Pasadyn, Christopher A. Bode
Abstract: A method and apparatus is provided for creating a process recipe based on a desired result. The method comprises providing at least one workpiece to a processing tool for processing, providing the desired result for the workpiece to the processing tool, and generating a recipe for processing the workpiece based on the desired result.
Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a memory controller that determines whether a complete frame is stored in the random access memory and also determines an amount of data available to be read from the oldest received frame. A host CPU is able to access this information and determine whether to read the data or read the data at a later time.
Abstract: A method and apparatus for handling split response transactions within a peripheral interface of an I/O node of a computer system. An apparatus includes a first buffer circuit coupled to receive packet commands from a requesting node. The first buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The apparatus also includes a bus interface circuit which may be configured to cause a bus cycle corresponding to a given packet command stored within the first buffer circuit to be initiated upon a peripheral bus. Further, the apparatus includes a second buffer circuit coupled to store the given packet command in response to receiving a split response from a target of the bus cycle.
Abstract: The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the transistor being comprised of a gate electrode, the bulk substrate being doped with a dopant material at a first concentration level. The device further comprises a first doped region formed in the bulk substrate, the first doped region being doped with a dopant material that is the same type as the bulk substrate dopant material, wherein the concentration level of dopant material in the first doped region is greater than the first dopant concentration level in the bulk substrate, the first doped region being substantially aligned with the gate electrode.
Type:
Application
Filed:
March 9, 2004
Publication date:
September 2, 2004
Applicant:
Advanced Micro Devices, Inc.
Inventors:
Andy C. Wei, Derick J. Wristers, Mark B. Fuselier
Abstract: A test system includes a switch emulator, a network test device, and an interface converter. The switch emulator is configured for transmitting first network data on a first media independent interface based on a first interface clock, and the network test device configured for transmitting second network data on a second media independent interface based on a second interface clock. The interface converter, having inverted media independent interfaces, is configured for transferring the first and second network data between the first and second media independent interfaces, and supplying the first and second interface clocks based on an external clock generated by the switch emulator. Hence, network data can be passed between the switch emulator and the network test device according to network protocols, even if the switch emulator is operating at relatively slow speeds.
Type:
Grant
Filed:
February 9, 2001
Date of Patent:
August 31, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Harand Gaspar, Shashank Merchant, Jiu An
Abstract: A method of manufacturing a semiconductor device, including depositing a gate oxide film over a substrate and conditioning the deposited gate oxide film using laser thermal annealing in a single process chamber, and depositing a gate electrode film over the conditioned gate oxide film.
Type:
Grant
Filed:
August 6, 2002
Date of Patent:
August 31, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Arvind Halliyal, Nicholas H. Tripsas, Mark T. Ramsbey
Abstract: An apparatus for testing an electrical device which includes fuses has a resilient, compressive, insulating base amounted to the underside of a thermal head. A plurality of conductive elements are mounted to the base in parallel relation. A number of these conductive elements are caused to be brought into contact with and bridge a fuse of the device when the thermal head is brought in dose proximity to the device. The conductive elements cause the fuse to be bridged, so that connection is provided between one side of the fuse and the other.
Abstract: A method of using high yielding spectra scatterometry measurements to control semiconductor manufacturing processes and systems for accomplishing same is disclosed. In one embodiment, the method comprises providing a library comprised of at least one target optical characteristic trace of a grating structure comprised of a plurality of gate stacks, the target trace corresponding to a semiconductor device having at least one desired electrical performance characteristic, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of gate stacks, illuminating at least one grating structure formed above said substrate, measuring light reflected off of the grating structure formed above the substrate to generate an optical characteristic trace for the formed grating structure, and comparing the generated optical characteristic trace to the target trace.
Type:
Grant
Filed:
February 28, 2002
Date of Patent:
August 31, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
James Broc Stirton, Kevin R. Lensing, Hormuzdiar E. Nariman, Steven P. Reeves