Patents Assigned to Advanced Micro Devices, Inc.
  • Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
    Patent number: 6764966
    Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William George En, Arvind Halliyal, Ming-Ren Lin, Minh Van Ngo, Chih-Yuh Yang
  • Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
    Patent number: 6764884
    Abstract: A method of manufacturing a FinFET device includes forming a fin structure on an insulating layer. The fin structure includes a conductive fin. The method also includes forming source/drain regions and forming a dummy gate over the fin. The dummy gate may be removed and the width of the fin in the channel region may be reduced. The method further includes depositing a gate material to replace the removed dummy gate.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bin Yu, Haihong Wang
  • Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents
    Patent number: 6764908
    Abstract: A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Daniel Kadosh, Derick J. Wristers, Qi Xiang, Bin Yu
  • Method for reducing gate line deformation and reducing gate line widths in semiconductor devices
    Patent number: 6764947
    Abstract: A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darin Chan, Douglas J. Bonser, Marina V. Plat, Marilyn I. Wright, Chih Yuh Yang, Lu You, Scott A. Bell, Philip A. Fisher
  • Structure and method for preventing UV radiation damage and increasing data retention in memory cells
    Patent number: 6765254
    Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer which comprises silicon-rich TCS nitride. Further, an oxide cap layer is situated over the UV radiation blocking layer. The structure might further comprise an antireflective coating layer over the oxide cap layer. The interlayer dielectric may comprise BPSG and the oxide cap layer may comprise TEOS oxide.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Angela Hui, Minh V. Ngo, Ning Cheng, Jaeyong Park, Jean Y. Yang, Hidehiko Shiraiwa, Rinji Sugino, Tazrien Kamal, Cinti X. Chen
  • Method and apparatus for dynamically enabling trace data collection
    Patent number: 6766258
    Abstract: A method includes identifying a degraded condition associated with the processing of a workpiece. At least one process tool associated with the degraded condition is identified. Trace data collection is enabled for the identified process tool. A system includes a processing system configured to process a workpiece and a tool monitor. The tool monitor is configured to identify a degraded condition associated with the processing of the workpiece, identify at least one process tool from the processing system associated with the degraded condition, and enable trace data collection for the identified process tool.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Edward C. Stewart, Susan Hickey
  • Passivation of nitride spacer
    Patent number: 6764912
    Abstract: The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Clayton Foster, Eric N. Paton, Matthew S. Buynoski, Qi Xiang, Paul R. Besser, Paul L. King
  • Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices
    Patent number: 6764920
    Abstract: A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides (510) for flash memories (devices M and N). An STI process is implemented to isolate flash memory devices (devices M and N) in the semiconductor structure (200). In the STI process, a nitride layer (210) is deposited over a silicon substrate (280). An STI region (290) is formed defining STI corners (240) where a top surface (270) of the silicon substrate (280) and the STI region (290) converge. The STI region (290) is filled with an STI field oxide and planarized until reaching the nitride layer (210). A local oxidation of silicon (LOCOS) is then performed to oxidize the top surface (270) of the silicon substrate adjacent to the STI corners (240).
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nian Yang, John Jianshi Wang, Unsoon Kim
  • FinFET-based SRAM cell
    Patent number: 6765303
    Abstract: A SRAM cell includes a single FinFET and two resonant tunnel diodes. The FinFet has multiple channel regions formed from separate fins. The resonant tunnel diodes may be formed from FinFET type fins. In particular, the resonant diodes may includes a thin, undoped silicon region surrounded by a dielectric. The SRAM cell is small and provides fast read/write access times.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Judy Xilin An, Matthew S. Buynoski
  • Shallow trench isolation for strained silicon processes
    Publication number: 20040137742
    Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 15, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Minh-Van Ngo, Qi Xiang, Paul R. Besser, Eric N. Paton, Ming-Ren Lin
  • FinFET device with multiple fin structures
    Patent number: 6762448
    Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-Ren Lin, Haihong Wang, Bin Yu
  • MOSFET with SiGe source/drain regions and epitaxial gate dielectric
    Patent number: 6762463
    Abstract: In accordance with the invention, a MOSFET includes a well, a channel formed in the well, a high K layer overlying the channel, a buffer layer overlying the high k layer, a gate overlaying the buffer layer, a blocking layer overlying the gate and two source/drain regions. In some embodiments the gate and the source/drain regions are silicon germanium.
    Type: Grant
    Filed: June 9, 2001
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hyeon-Seag Kim
  • Speculative bus arbitrator and method of operation
    Patent number: 6763415
    Abstract: A bus interface unit for transferring data between a plurality of bus devices. The bus interface unit comprises: 1) a destination prediction circuit for predicting a predicted destination bus device associated with a first incoming bus access request received from a requesting one of the plurality of bus devices; 2) an arbitration circuit coupled to the destination prediction circuit and for arbitrating the first incoming bus access request based on the predicted destination bus device; and 3) an address determination circuit for calculating an actual destination bus device at least partially simultaneously with the arbitration of the first incoming bus access request and determining if the calculated actual destination bus device matches the predicted destination bus device.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Brett A. Tischler
  • Structure, system, and method for assessing electromigration permeability of layer material within interconnect
    Patent number: 6762597
    Abstract: For determining electromigration permeability of a layer material, a test line, a feeder line, and a cathode line of an interconnect test structure are formed with current flowing from the test line through the feeder line to the cathode line. A no-flux structure is disposed between the cathode line and the feeder line, and the layer material is disposed between the feeder line and the test line. A respective current density and length product of the feeder line and the test line is respectively less than and greater than a respective critical Blech length constant. An occurrence of a void within the feeder line or the test line indicates that the layer material is permeable or impermeable.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christine Hau-Riege, Stefan Hau-Riege, Amit P. Marathe
  • Operating a processing tool in a degraded mode upon detecting a fault
    Patent number: 6763278
    Abstract: A method and apparatus is provided for operating a processing tool in a degraded mode upon detecting a fault and in accordance with one or more business rules. The method comprises detecting a fault associated with a processing tool capable of processing one or more workpieces and operating the processing tool in a degraded mode in response to detecting the fault.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Elfido Coss, Jr., Michael R. Conboy, Sam H. Allen, Jr.
  • System and method for control of hardmask etch to prevent pattern collapse of ultra-thin resists
    Patent number: 6762133
    Abstract: The present invention relates to systems and methods for mitigating pattern collapse in ultra-thin resist processing. In one embodiment, the present invention relates to etching extremely fine patterns into a hardmask immediately after developing an ultra-thin resist, wherein the resist is not dried.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Ramkumar Subramanian, Khoi A. Phan
  • Method and apparatus for proactive dispatch system to improve line balancing
    Patent number: 6763277
    Abstract: A method, apparatus, and system is provided for a proactive dispatch system to improve line balancing. At least one request for processing a semiconductor wafer is received. A line-balancing analysis based upon the request is performed. At least one semiconductor wafer based upon the line-balancing analysis is processed.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sam H. Allen, Jr., Michael R. Conboy, Jason A. Grover
  • Narrow fin FinFET
    Patent number: 6762483
    Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Haihong Wang, Bin Yu
  • Apparatus and method for electrochemical metal deposition
    Patent number: 6761812
    Abstract: In an electroplating apparatus for semiconductor wafers, the currents to each of a plurality of contact portions contacting the wafer edge are individually adjustable and/or a parameter indicative of the current flow in each contact portion may be determined. Moreover, for precise control of the currents, means are provided for monitoring the currents.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Gerd Marxsen
  • Stacked polysilicon layer for boron penetration inhibition
    Patent number: 6762454
    Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a stacked polysilicon layer formed on a dielectric layer. The stacked polysilicon layer inhibits the diffusion of boron in the dielectric layer and the penetration of boron into the dielectric layer and the semiconductor substrate.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Effiong Ibok, Joong S. Jeon, Arvind Halliyal, Minh Van Ngo