Abstract: Numerous methods for forming various semiconductor structures are disclosed. In one embodiment, a layered dielectric structure of alternating sub-layers of a first dielectric material and a second dielectric material is formed on a suitable semiconductor substrate. In this embodiment, the layered dielectric structure comprises an alternating pattern of at least two sub-layers of a first dielectric material which is a high-K dielectric material and at least one layer of a second dielectric material which is a standard-K dielectric material, wherein at least one of the one or more second dielectric material sub-layers contain nitrogen implanted therein using a nitridation step.

Abstract: The present invention is generally directed to various methods of controlling Vss implants on memory devices, and a system for performing same. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate, measuring at least one physical characteristic of at least one of the trenches and determining at least one parameter of a VSS implant process to be performed on the substrate based upon the measured at least one physical characteristic of at least one trench.

Abstract: The present invention is generally directed to method of dynamically enabling additional sensors based upon initial sensor data, and a system for accomplishing same. In one illustrative embodiment, the method comprises initiating a process operation in a process tool, determining if an abnormal process event has occurred in the process operation based upon data sensed by at least one control sensor, enabling at least one additional sensor to acquire additional data related to the process operation if an abnormal process event is determined to have occurred and obtaining data from the enabled additional sensor.

Abstract: A method of using scatterometric techniques to control stepper process is disclosed. In one illustrative embodiment, the method comprises providing a library of optical characteristic traces, each of which corresponds to a grating structure comprised of a plurality of features having a known profile, and forming a plurality of grating structures in a layer of photoresist, each of said formed grating structures being comprised of a plurality of features having an unknown profile.

Abstract: A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Abstract: In general, the present invention is directed to methods of using weight or mass measurements to control various semiconductor manufacturing processes, and systems for accomplishing same. One illustrative method comprises providing a substrate, performing a deposition process to form a process layer above the substrate, determining a weight or mass of the process layer formed above the substrate, and controlling at least one parameter of the deposition process based upon the determined weight or mass of the process layer. One illustrative system in accordance with the present invention comprises a deposition tool for performing a deposition process to form a process layer above a substrate, a pressure sensor in contact with the substrate for sensing a pressure induced as a result of the process layer formed above the substrate, and a controller for controlling at least one parameter of the deposition process based upon the sensed pressure.

Abstract: The present invention is generally directed to various methods of controlling wet chemical processes in forming metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal while the wet chemical process is being performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal.

Abstract: A method and apparatus for determining a possible cause of a fault in a semiconductor fabrication process. The method includes determining a first fault in a first processing tool executing under first operating conditions and determining a second fault in a second processing tool executing under second operating conditions. The method further includes identifying a possible source of the second fault based on at least the first operating conditions of the first processing tool.

Abstract: A method for measuring porosity of nanoporous materials is provided using atomic force microscopy (AFM). A surface topology map with sub-atomic resolution is created using AFM wherein the pore shape and size can be determined by measuring the pores that intersect the top or fracture surface. For porous materials requiring more accurate measurements, small scan areas with slow scan speed and fine AFM tips are used and a general estimation on distribution can be made from a sample area.

Abstract: A method includes scheduling a plurality of workpieces for processing by a plurality of tools. Each workpiece has an associated priority. The processing in at least one of the tools is controlled in accordance with a process control model. A process control request associated with the controlling of the tool is generated. The priorities of at least a subset of the workpieces are determined based on the process control request. A manufacturing system includes a plurality of tools for processing workpieces, a dispatch unit, and a process control unit. The dispatch unit is configured to schedule a plurality of workpieces for processing by the tools. Each workpiece has an associated priority. The process control unit is configured to control the processing in at least one of the tools in accordance with a process control model and generate a process control request associated with the controlling of the tool.

Abstract: In one illustrative embodiment, the method involves forming a ring oscillator that includes a first grating structure comprised of a plurality of gate electrode structures for a plurality of N-channel transistors and a second grating structure comprised of a plurality of gate electrode structures for a plurality of P-channel transistors, and measuring the critical dimension and/or profile of at least one of the gate electrode structures in the first grating structure and/or the second grating structure using a scatterometry tool. In another embodiment, the method further involves forming at least one capacitance loading structure, comprised of a plurality of features, as a portion of the ring oscillator, and measuring the critical dimension and/or profile of at least one of the features of the capacitance loading structure using a scatterometry tool.

Abstract: Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer. In this connection, low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers are disclosed, as well as methods of making the low k material layers.

Abstract: An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first and a second end separated by a programmable link. The first end of the one-time programmable element is coupled to a power supply voltage node in the package. The second end of the programmable element may be coupled to an external package connection (e.g., a package pin) and/or to an internal package node that connects to an input terminal of the integrated circuit die when the integrated circuit die is mounted in the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

Abstract: An interconnect structure which has improved stress migration reliability is disclosed. According to one exemplary embodiment, the interconnect structure comprises a top interconnect metal layer, at least one via and a bottom interconnect metal layer. The bottom interconnect metal layer comprises at least one finger. The at least one via electrically connects the top interconnect metal layer to the at least one finger. The finger width of the at least one finger is less than a bottom layer width of the bottom interconnect metal layer. In another embodiment, a method for fabricating the above interconnect structure is disclosed.

Abstract: The present invention provides a method for forming a low-k dielectric structure on a substrate 10 that includes depositing, upon the substrate, a dielectric layer 12. A multi-film cap layer 18 is deposited upon the dielectric layer. The multi-film cap layer includes first 181 and second 182 films, with the second film being disposed between the dielectric layer and the first film. The first film typically has a removal rate associated therewith that is less than the removal rate associated with the second film. A deposition layer 20 is deposited upon the multi-film cap layer and subsequently removed. The properties of the multi-film cap layer are selected so as to prevent the dielectric layer from being exposed/removed during removal of the deposition film. In this manner, a deposition layer, having variable rates of removal, such as copper, may be planarized without damaging the underlying dielectric layer.

Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Abstract: Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer. The active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween. The source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon. The silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.

Abstract: A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.

Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.