Abstract: A method of manufacturing a semiconductor device, including depositing a gate oxide film over a substrate and conditioning the deposited gate oxide film using laser thermal annealing in a single process chamber, and depositing a gate electrode film over the conditioned gate oxide film.

Abstract: An apparatus for testing an electrical device which includes fuses has a resilient, compressive, insulating base amounted to the underside of a thermal head. A plurality of conductive elements are mounted to the base in parallel relation. A number of these conductive elements are caused to be brought into contact with and bridge a fuse of the device when the thermal head is brought in dose proximity to the device. The conductive elements cause the fuse to be bridged, so that connection is provided between one side of the fuse and the other.

Abstract: A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current profile is recorded. A comparison of current profiles obtained for the two types of structures may indicate the presence and/or extent of STI corner effects. More specifically, a steeper slope for a normalized current versus time plot for an STI edge intensive structure (500) compared to a slope of a normalized plot of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness is observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

Abstract: There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

Abstract: An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store the results of the tests. The results may be transmitted from the memory device. The integrated memory self-tester may be initiated via a test signal, be self initiated periodically, or be initiated by other means.

Abstract: A differentail amplifier with input gate oxide breakdown avoidance amplifies a difference between two signals while maintaining voltage drops across transistor utilized in the differential amplifier to below a gate oxide breakdown level. A pull up structure added to a traditional differential amplifier allows the circuit to be utilized in IO pads of an integrated circuit and to be composed of thin oxide transistor normally only found in the core circuitry of the integrated circuit and. The pull up structure is composed of three thin oxide transistors, the first transistor is connected in series with the other two, and the other two connected in parallel with respect to each other.

Abstract: In one embodiment, a polarization measuring device comprises a light source, a reticle positioned below the light source, an opaque frame having a single aperture, the opaque frame positioned below the reticle, a lens positioned below the opaque frame, and a wafer having photoresist on its surface. The aperture of the frame allows no more than a first light ray to pass from the light source through the reticle and the lens onto a first surface point on the photoresist. The aperture of the frame also allows no more than a second light ray to pass from the light source through the reticle and the lens onto a second surface point on the photoresist. The degree of polarization of the light source can be determined from the first amount of light absorbed at the first surface point and the second amount of light absorbed at the second surface point.

Abstract: A novel method and system for fabricating integrated circuit devices is disclosed herein. In one embodiment, the method comprises determining at least one electrical performance characteristic of a plurality of semiconductor devices formed above at least one semiconducting substrate, providing the determined electrical performance characteristics to a controller that determines, based upon the determined electrical characteristics, across-substrate variations in an exposure dose of a stepper exposure process to be performed on at least one subsequently processed substrate, and performing the stepper exposure process comprised of the across-substrate variations in exposure dose on the subsequently processed substrates.

Abstract: A method for adaptively scheduling tool maintenance includes controlling an operating recipe of a tool using a plurality of control actions, monitoring the control actions to identify a degraded tool condition, and automatically initiating a tool maintenance recommendation in response to identifying the degraded tool condition. A manufacturing system includes a tool, a process controller, and a tool health monitor. The tool is adapted to process a workpiece in accordance with an operating recipe. The process controller is adapted to control the operating recipe of the tool using a plurality of control actions. The tool health monitor is adapted to monitor the control actions to identify a degraded tool condition and automatically initiate a tool maintenance recommendation in response to identifying the degraded tool condition.

Abstract: One aspect of the present invention relates to a system and method for detecting defects on a reticle by inspecting latent images printed on a resist wafer by the reticle. The system includes a wafer having a printed photoresist layer formed thereon, a latent image inspection system connected to the wafer exposure system for examining the printed photoresist layer in order to determine whether a reticle employed to print the photoresist layer is defective, and a processor for receiving data from the inspection system in order to verify the presence of defects on the reticle. The method involves printing a first latent image, a second latent image, and a third latent image on a resist wafer using a reticle, and comparing the three latent images to one another to determine whether the reticle is defective. Comparison of the latent images may be facilitated by employing an optical system programmed to perform such comparisons.

Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a phosphine plasma produced in PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a copper containing layer within the trench.

Abstract: An apparatus is provided for providing security in a computer system. The apparatus comprises an address generator, a multi-level lookup table, and a cache. The address generator is adapted for producing an address associated with a memory location in the computer system. The multi-level lookup table is adapted for receiving at least a portion of said address and delivering security attributes stored therein associated with said address, wherein the security attributes are associated with each page of memory in the computer system. The cache is a high-speed memory that contains a subset of the information contained in the multi-level lookup table, and may be used to speed the overall retrieval of the requested security attributes when the requested information is present in the cache.

Abstract: A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.

Abstract: A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The alignment information may be, for example, instruction pointers, each of which directly locates a corresponding instruction within a plurality of instruction bytes fetched in response to the fetch address. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Fetch addresses may be searched against the fetch addresses stored in the multiple entries, and if a match is detected the corresponding instruction pointers may be used.

Abstract: Ultra-thin gate oxides are formed by exposing the upper surface of a substrate to a pulsed laser light beam in an atmosphere containing oxygen. Embodiments include exposing a silicon substrate to a pulsed laser light beam at a radiant fluence of 0.1 to 0.8 joules/cm2 for 1 to 10 nanoseconds to form a gate oxide layer having a thickness of 3 Å to 8 Å, e.g., 3 Å to 5 Å.

Abstract: In programming the threshold voltage of a memory cell transistor having a substrate, a gate insulator on the substrate, a floating gate on the gate insulator, an insulating layer on the floating gate, and a control gate on the insulating layer, and a source and drain in the substrate, a voltage difference is applied between the drain and source of the transistor and negative voltage is applied to the substrate of the transistor. An increasing voltage is applied to the control gate of the transistor, and, during application of that increasing voltage, a succession of verification tests are undertaken at a corresponding succession of times separated by chosen time intervals to verify if the transistor has been programmed to a chosen threshold voltage.

Abstract: A circuit for demodulating a modulated carrier includes a sampler receiving the modulated carrier signal and generating a digital carrier signal represented by a sequence of sample values in accordance with a clock signal at a first sampling frequency. A complex mixer frequency shifts the digital carrier signal by a frequency equal to one fourth the sampling frequency to generate a frequency shifted data signal with a sampling rate at the first sampling frequency. A decimation circuit generates four decimated signals from the frequency shifted signal, each at a decimated sampling rate. A resampling circuit generates a data signal at the decimated sampling rate and at a phase independent of the clock signal.

Abstract: A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.

Abstract: Various microscopy probes and methods of fabricating the same are provided. In one aspect, a method of fabricating a microscopy probe is provided that includes providing a member and forming a first film on the member. The first film fosters growth of carbon nanotubes when exposed to a carbon-containing compound. A second film is formed on the first film. The second film has an opening therein that exposes a portion of the first film. A carbon nanotube is formed on the exposed portion of the first film.

Abstract: The present invention is a method of communicating within a phone line LAN. The method includes the assignment of a unique VLAN ID to each node of a VLAN. A VLAN header is attached at a source node of the frame to each frame to be communicated within the VLAN. The VLAN header contains identification information associated with the VLAN. The VLAN header is inserted by a network interface device driver into a frame header. Data communication within the VLAN is controlled at the nodes of the VLAN by examining incoming frames for the presence or absence of the VLAN header. The VLAN header is stripped at the destination nodes of the VLAN from the frame header and a remaining part of the frame is passed to a software device driver arrangement.